How can we compare two different designs that perform same task (e.g. processing a 256x256 image) and both implemented on different FPGAs, in terms of processing time(seconds)?
For example one of them is on Virtex-5 and other one is on Virtex-7. I know that these two families have different specifications in terms of speed grade, available resources, architecture etc. So I thought it is not convenient to do this comparison (a fair way to do it would be comparing clock cycle count). But I wanted to ask it because I came upon some papers which does this sort of thing. (e.g. compares a design implemented on Virtex-5 with a design implemented on Virtex-7 and claims that his/her design/implementation is faster in terms of seconds)
Edit: I am normally doing this comparison by mapping my design onto the same family of FPGA used by the competitor.
A lot of time passed since I asked this question but I still feel that I have failed to describe the situation correctly.
You can achieve better timing results if you use technologically better FPGAs. Critical term is TIMING here. Do not assume that I will set the same timing constraint for both FPGAs. This is not the case. Please consider the question like that:
For Virtex-5: timing constraint is set to 100 MHz and it is met (T. constraint 105 Mhz Fails).
For Virtex-7: timing constraint is set to 150 MHz and it is met (155 Mhz fails). So I'm trying to find out the best achievable frequency for the device. Virtex-5 and Virtex-7 are just for the example. They may not have such a performance gap.
My architecture achieves better result if I use Virtex-7.
So now imagine that someone implements a circuit that performs the same task as my design.
He/She implements the circuit for Virtex-7 and achieves a max frequency of 130 MHz.
He then compares this result (WITHOUT implementing it for Virtex-5) with my Virtex-5 result (100 MHz) and concludes that his/her architecture is better. Assume that clock cycles are equal for both circuits.
In my opinion, if such a comparison to be made; it should be done by using same family of FPGA device. Otherwise it is not a fair comparison. Purpose of this question is to find out if there are exceptions to that.