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How can we compare two different designs that perform same task (e.g. processing a 256x256 image) and both implemented on different FPGAs, in terms of processing time(seconds)?

For example one of them is on Virtex-5 and other one is on Virtex-7. I know that these two families have different specifications in terms of speed grade, available resources, architecture etc. So I thought it is not convenient to do this comparison (a fair way to do it would be comparing clock cycle count). But I wanted to ask it because I came upon some papers which does this sort of thing. (e.g. compares a design implemented on Virtex-5 with a design implemented on Virtex-7 and claims that his/her design/implementation is faster in terms of seconds)

Edit: I am normally doing this comparison by mapping my design onto the same family of FPGA used by the competitor.

Edit2:

A lot of time passed since I asked this question but I still feel that I have failed to describe the situation correctly.

You can achieve better timing results if you use technologically better FPGAs. Critical term is TIMING here. Do not assume that I will set the same timing constraint for both FPGAs. This is not the case. Please consider the question like that:

For Virtex-5: timing constraint is set to 100 MHz and it is met (T. constraint 105 Mhz Fails).

For Virtex-7: timing constraint is set to 150 MHz and it is met (155 Mhz fails). So I'm trying to find out the best achievable frequency for the device. Virtex-5 and Virtex-7 are just for the example. They may not have such a performance gap.

My architecture achieves better result if I use Virtex-7.

So now imagine that someone implements a circuit that performs the same task as my design.

He/She implements the circuit for Virtex-7 and achieves a max frequency of 130 MHz.

He then compares this result (WITHOUT implementing it for Virtex-5) with my Virtex-5 result (100 MHz) and concludes that his/her architecture is better. Assume that clock cycles are equal for both circuits.

In my opinion, if such a comparison to be made; it should be done by using same family of FPGA device. Otherwise it is not a fair comparison. Purpose of this question is to find out if there are exceptions to that.

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closed as unclear what you're asking by PeterJ, Daniel Grillo, Dave Tweed Mar 4 '16 at 19:39

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    \$\begingroup\$ It's kind of meaningless. You should know theoretically from your architecture how many clock cycles specific calculation is taking. And then just multiply it by the clock duration. \$\endgroup\$ – Eugene Sh. Aug 19 '15 at 15:30
  • \$\begingroup\$ @EugeneSh. A more correct question would be "How" more than "Can"... Because sure you can compare the time of execution \$\endgroup\$ – MathieuL Aug 19 '15 at 15:42
  • \$\begingroup\$ You are right, thank you. @EugeneSh. That is what I normally thought but I wanted to learn if there is some valid reasons or some exceptions to do this kind of comparison. \$\endgroup\$ – Chief Aug 19 '15 at 15:57
  • \$\begingroup\$ @Chief Valid reasons could be some very complex algorithm, difficult to analyze in these terms, or some non-deterministic input data. If both are not the case, a theoretical calculation should be sufficient. \$\endgroup\$ – Eugene Sh. Aug 19 '15 at 16:00
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    \$\begingroup\$ @FarhadA You are correct if both implementations done on the same FPGA (same family, same vendor etc.). We can than compare latency and operating frequency of two designs and determine better of the two. So for example if both of them are implemented on Virtex-5 FPGA and max operating freq. for both of them is 50 MHz and if the execution times are 5.04 ns and 9.34 ns respectively, we can say that 5.04ns is faster and that implementation is better in terms of speed. But as I indicated in the question, comparing Virtex-7 with Virtex-5 using only the execution time seems unfair. \$\endgroup\$ – Chief Aug 26 '15 at 14:16