Xilinx offers an Integrated Logic Analyzer (ILA) / called ChipScope. Altera's Quartus II comes with SignalTap - an equivalent solution.
As an advance user\$^1\$, I'm using ChipScope as pre-compiled netlists. These *.xco and *.ngc files are generated via CoreGen and embedded into the design hierarchy by VHDL entity instances.
I would like to equip a Quartus II example project in the same way:
- configure analyzer cores
- compile them to a netlist
- embed them into the design and connect the analyzer ports to my list of observable signals
- provide a default SignalTap configuration file
Is there an equivalent to Xilinx's ICON, VIO, ILA IP-Cores in Altera's SignalTap?
Here are the Xilinx steps compared to list:
- Configure an ILA core in CORE generator (=> *.xco file)
- While saving the*.xco file, it's compile to a netlist (*.ngc, *.ncf, ...)
- A wrapper *.vhdl file is provided, which is replace by the netlist in the translate step
- each ILA provides a *.cdc file, which can be imported into the ChipScope project to load the signal names
\$^1\$ Pre-compiled ILAs save synthesis time; can be configured with complex cross-triggers; can be used with VIOs (Virtual-Input-Output cores).