Xilinx offers an Integrated Logic Analyzer (ILA) / called ChipScope. Altera's Quartus II comes with SignalTap - an equivalent solution.

As an advance user\$^1\$, I'm using ChipScope as pre-compiled netlists. These *.xco and *.ngc files are generated via CoreGen and embedded into the design hierarchy by VHDL entity instances.

I would like to equip a Quartus II example project in the same way:

  1. configure analyzer cores
  2. compile them to a netlist
  3. embed them into the design and connect the analyzer ports to my list of observable signals
  4. provide a default SignalTap configuration file

Is there an equivalent to Xilinx's ICON, VIO, ILA IP-Cores in Altera's SignalTap?


Here are the Xilinx steps compared to list:

  1. Configure an ILA core in CORE generator (=> *.xco file)
  2. While saving the*.xco file, it's compile to a netlist (*.ngc, *.ncf, ...)
  3. A wrapper *.vhdl file is provided, which is replace by the netlist in the translate step
  4. each ILA provides a *.cdc file, which can be imported into the ChipScope project to load the signal names

\$^1\$ Pre-compiled ILAs save synthesis time; can be configured with complex cross-triggers; can be used with VIOs (Virtual-Input-Output cores).


Yes, for most of them there are.

You can instance SignalTap into your design adding a .STP file to your project OR instancing and configuring the explicit SignalTap block in your design.

For the first option (the simplest and non intrusive), just use the graphical interface provided For the second one follow the instruction in this help topic. http://quartushelp.altera.com/14.0/mergedProjects/program/ela/ela_pro_setup.htm Look for the item "To use the IP Catalog to create a SignalTap II instance"

In addition to SignalTap (logic analyzer) you can find other debugging useful IP, like Memory Contents Editor, to allow you edit and read the memory blocks instanced in your design while your circuit is running. And there some additional tools to manamge signal integrity on tranceiver capable dies.

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