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I have a state diagram that is consisted of 3 states and in reset it comes to state s0 then if an event happen on start signal goes to state 2 and statye there for 15 clock sycle and then after that goes to state 3 and then back to state s0. My question is that when VHDL coding how could I do the 15 clock delay of state 2. I know that a counter needs to be there but it is not clear for me how to do the VHDL coding. Could any one please give me some help. Thank you

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  • \$\begingroup\$ I write a VHDL code for a counter that is a down counter and I have written a process for output logic of the state machine but I dont know how I could relate these two to each other \$\endgroup\$ – user83736 Aug 21 '15 at 13:35
  • \$\begingroup\$ A pure FSM can't have a counter. Counter is FSM itself. If it is counting up to N, it will have N (or N-1) states. This is the theory. \$\endgroup\$ – Eugene Sh. Aug 21 '15 at 13:38
  • \$\begingroup\$ Then I should you 2 FSM for that? \$\endgroup\$ – user83736 Aug 21 '15 at 13:39
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    \$\begingroup\$ I though of using one process for the fsm itself and another fsm for the timing which would result in 2 FSM ? \$\endgroup\$ – user83736 Aug 21 '15 at 13:41
  • \$\begingroup\$ Well, you don't have to design it as a pure FSM. As I said, it's a theory. \$\endgroup\$ – Eugene Sh. Aug 21 '15 at 13:42
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Assuming you're not doing the "theoretically pure" method of programming a FSM in VHDL, just do something simple like this:

fsmCount: process(clk, reset)
    begin
        if reset = '1' then
            --Reset code here

        elsif(clk'event and clk = '1') then    --on the rising edge of the clock

            case state is
                when s0 =>
                    --VHDL for s0 

                when s1 =>  
                    --VHDL for s0 

                when s2 =>
                    s_counter <= s_counter + 1;    --increment a counting signal
                    if s_counter = CLOCK_DELAY_15_CONSTANT then
                         --do what you want here when you hit your delay
                         s_counter <= '0';
                    else
                         state <= s2;        --if your delay isn't reached, stay in this state
                    end if;
            end case;
    end if;
end process fsmCount;

I'm just answering the state: s2 portion, I'll let you handle the rest of the logic you require in the rest of the FSM.

You will also need to declare some signals and constants in your architecture section:

The variable "state" is an enumeration of the different states you need (i.e.: s0, s1, s2).

Then "s_counter" is some signal of some bits wide that you declare.

"CLOCK_DELAY_15_CONSTANT" is a constant value that you decide is necessary for your desired delay. Which sounds like it's just 15 clock cycles, so it's just 15 in that case.

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This is an example, on how a FSM can control a counter. If the second state is entered, the counter counts up until 15, then the FSM goes to the next state. The counter is reset in every other state.

Declarations:

type T_STATE is (ST_IDLE, ST_SECOND, ST_FINISHED);

signal State        : T_STATE    := ST_IDLE;
signal NextState    : T_STATE;

signal Counter_en   : STD_LOGIC;
signal Counter_us   : UNSIGNED(3 downto 0)    := (others => '0');

Logic:

process(Clock)
begin
  if rising_edge(Clock) then
    State  <= NextState;

    if (Counter_en = '0') then
      Counter_us <= (others => '0');
    else
      Counter_us <= Counter_us + 1;
    end if;
  end if;
end process;

process(State, Input1, Counter_us)
begin
  -- default assignments
  NextState     <= State;
  Counter_en    <= '0';

  case State is
    when ST_IDLE =>
      -- do something

    when ST_SECOND =>
      Counter_en    <= '1';

      if (Counter_us = 15) then
        NextState   <= ST_FINISHED;
      end if;

    when ST_FINISHED =>
      -- do something

  end case;
end process;

Is is only one possible example on how FSMs/Counters can interact.

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  • \$\begingroup\$ That was really helpful. \$\endgroup\$ – user83736 Aug 21 '15 at 16:46

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