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I'm reading an assembly language book. The problem with this book is that it tries to explain how a ram works with a CPU, but it doesn't explain in depth.

I would like to know how a memory cell, address line, and data pin work when storing or retrieving data.

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All memory cells have their level, either 0 or 1. The CPU tells the memory device which cells it needs the binary values of, and supplies this address to the memory device. Inside the memory device the address is decoded in a row and column address, and the cell at that position in the matrix is allowed to gets its data to the databus, i.e. the data pin.

Let's say we have an 8-bit address 01100101. This will be split up in a row address 0110 (the high order nibble) and a column address 0101 (the low order nibble). The row address selects row #06, so all cells connected to this row will have their data ready. The column address selects the cell at column #05 of this row, so that finally only one single cell is allowed to place its data to the output pin.

Storing data follows the same pattern: only one row is selected, and the cell at the given column in that row will get the data present on the pin stored.

This is for 1 bit. The operation occurs for the full data word width simultaneously, so if you have a byte-wide memory, 8 bits are retrieved and their value placed on 8 databus pins.

edit
This picture should help you seeing things better:

memory array

This is a representation of a DRAM array, where data is stored in the charge of the capacitors, each capacitor is one bit. The row part of the address (here A1..A0) selects a row, which means they activate all FETs on that row, so that the levels of the capacitors for that row become available on their corresponding column. Then the column address selection block, controlled by the other part of the address, A3..A2, selects the one bit which we want the data from.

DRAM is easy to build, but has a nasty disadvantage: reading the data discharges the capacitor, so the data is lost. To counter this DRAM has sense amplifiers, which detect the current memory cell status and refresh it when read. In addition this refresh has to be done periodically because the capacitors' charge will leak away even when the memory isn't read. The need for refresh circuitry is easily compensated for thanks to the DRAM's cells' compactness.

SRAM uses a couple of transistors to store the data, and it isn't volatile in the way DRAM is (though the data is still gone when you switch the power off). With EEPROM and Flash the data is stored in the (insulated) floating gate of a FET, and therefore it won't lose its data when power is switched off.


Further reading:
This answer about data retention in Flash memory.

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  • \$\begingroup\$ // I really appreciate your answer. May I ask a new question? Where did you learn it? I still don't understand it fully...may be because I can't visualize it. Do you have an image or book that I can refer to? \$\endgroup\$ – Moon Aug 27 '11 at 10:30
  • \$\begingroup\$ @Moon - learned it long ago in college. I think my course will have had pictures, but I don't have that course anymore (it was the time of everything on paper!). I'll see if I can find a good picture of it, and I'll add it to my answer if I find one. \$\endgroup\$ – stevenvh Aug 27 '11 at 10:36
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    \$\begingroup\$ college is not necessarily required to understand it, but you do need to understand the fundamentals of resistors, caps, and networks, and a functional understanding of how the various kinds of transitors work. I wonder if and how the Petzold book CODE covers the subject, might be worth thumbing through at a library or bookstore. \$\endgroup\$ – old_timer Aug 27 '11 at 14:20
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    \$\begingroup\$ I would HIGHLY recommend going through "from nand to tetris" if you want to grok the internals of computing. By the time you're half way through the book, you'll have built yourself a working CPU and RAM. It's a quick read if you already have some requisite knowledge, but it doesn't leave a step out if you don't. \$\endgroup\$ – James M. Lay Mar 26 '16 at 20:17

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