Here's the simple verilog code that contains WR_n signal. This signal (net) is not explicitly assigned to a LOC (pin) in the .ucf file. The design implements without any errors. I would assume that the WR_n net is assigned automatically to a pin. How do I know which pin is that?
module BasicCounter( input PCLK, input RESET, output reg WR_n, output [31:0] DQ, output [7:0] LED ); reg [31:0] Counter; // Put key signals on LEDs for DEBUG, ~ since LED is ON when signal is low assign LED = ~Counter[31:24]; assign DQ = Counter; always @ (posedge PCLK or posedge RESET) begin if (RESET) begin WR_n <= 1; // Disable writes Counter <= 0; end else begin WR_n <= 0; Counter <= Counter + 1; end end endmodule
And this is how the report menu looks like: