How is the signal assigned to a pin by default

Question

Here's the simple verilog code that contains WR_n signal. This signal (net) is not explicitly assigned to a LOC (pin) in the .ucf file. The design implements without any errors. I would assume that the WR_n net is assigned automatically to a pin. How do I know which pin is that?

module BasicCounter(
input PCLK,
input RESET,
output reg WR_n,
output [31:0] DQ,
output [7:0] LED
);

reg [31:0] Counter;

// Put key signals on LEDs for DEBUG, ~ since LED is ON when signal is low
assign LED = ~Counter[31:24];
assign DQ = Counter;

always @ (posedge PCLK or posedge RESET) begin
if (RESET) begin
    WR_n <= 1;      // Disable writes
    Counter <= 0;
end
else begin
    WR_n <= 0;
    Counter <= Counter + 1;
end
end
endmodule

And this is how the report menu looks like:

Answer 1

For CPLDs:

When you run the Xilinx ISE design flow, reports are generated. The report summary page, contains an item called Pin List.

I don't know how to distinguish located and unlocated pins in this report.

Here is an example report with one LED output, driven by a T-FF.

(clickable)

For FPGAs:

When you run the Xilinx ISE design flow, reports are generated. The report summary page, contains an item called Pinout Report.

Here you can see located (specified in UCF) and unlocated pins. An pin with a signal name, but not located is a pin, which was located by the mapper.

(clickable)

The map report contains also a section for I/O resources.

IO Utilization:
  Number of bonded IOBs:         22 out of     218   10%
    Number of LOCed IOBs:        22 out of      22  100%
    IOB Flip Flops:               6

What is what?
- bonded IOBs => all pins
- LOCed IOBs => pin specified in the *.ucf file
- IOB Flip Flops => I/O cells using the embedded flip flop