Here's the simple verilog code that contains WR_n signal. This signal (net) is not explicitly assigned to a LOC (pin) in the .ucf file. The design implements without any errors. I would assume that the WR_n net is assigned automatically to a pin. How do I know which pin is that?

module BasicCounter(
input PCLK,
input RESET,
output reg WR_n,
output [31:0] DQ,
output [7:0] LED

reg [31:0] Counter;

// Put key signals on LEDs for DEBUG, ~ since LED is ON when signal is low
assign LED = ~Counter[31:24];
assign DQ = Counter;

always @ (posedge PCLK or posedge RESET) begin
if (RESET) begin
    WR_n <= 1;      // Disable writes
    Counter <= 0;
else begin
    WR_n <= 0;
    Counter <= Counter + 1;

And this is how the report menu looks like:

enter image description here

  • \$\begingroup\$ You can grep for the name of the pin in the .pad report produced by par. \$\endgroup\$ – IanJ Oct 8 '15 at 23:15

For CPLDs:

When you run the Xilinx ISE design flow, reports are generated. The report summary page, contains an item called Pin List.

I don't know how to distinguish located and unlocated pins in this report.

Here is an example report with one LED output, driven by a T-FF.

enter image description here

For FPGAs:

When you run the Xilinx ISE design flow, reports are generated. The report summary page, contains an item called Pinout Report.

Here you can see located (specified in UCF) and unlocated pins. An pin with a signal name, but not located is a pin, which was located by the mapper.

enter image description here

The map report contains also a section for I/O resources.

IO Utilization:
  Number of bonded IOBs:         22 out of     218   10%
    Number of LOCed IOBs:        22 out of      22  100%
    IOB Flip Flops:               6

What is what?
- bonded IOBs => all pins
- LOCed IOBs => pin specified in the *.ucf file
- IOB Flip Flops => I/O cells using the embedded flip flop

  • \$\begingroup\$ My report does not look like yours... I just posted the screenshot in the undated question. \$\endgroup\$ – Nazar Aug 21 '15 at 20:36
  • \$\begingroup\$ @Naz OH, you are using a CPLD ... a CoolRunner2? There should be an equivalent report. My screenshot is from the FPGA flow :). \$\endgroup\$ – Paebbels Aug 21 '15 at 20:38
  • \$\begingroup\$ I seem to find the pin report, but there is no signal named WR_n. Very strange. \$\endgroup\$ – Nazar Aug 21 '15 at 20:42
  • \$\begingroup\$ @Naz I added a CPLD version of the Pin Report. I didn#t specify a pin location. My signal got placed at pin 143. \$\endgroup\$ – Paebbels Aug 21 '15 at 20:50
  • \$\begingroup\$ Yep. That's right. I have been looking for the WR_n signal, but it's not present there. this code is from the Example kit. I opened the CPLD Projects/Counter1/counter1.xise but I can not understand why I have signals in the report that do not exist in the source code, as well as the signals that are in the source code are not in the report. \$\endgroup\$ – Nazar Aug 21 '15 at 21:04

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