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If you want to read from the I2C bus you have to:

  1. Send start condition
  2. Send 7 bit slave address with R/W being a '0' which indicates a write
  3. Send register number where you want to read from
  4. Send start condition again
  5. Send 7 bit slave address with R/W being a '1' which indicates a read
  6. Slave sends data to master and master will send an ACK after each byte
  7. When done, the master sends a stop condition

Why isn't it done like this:

  1. Send start condition
  2. Send 7 bit slave address with R/W being a '1' which indicates a read
  3. Send register number where you want to read from
  4. Slave sends data to master and master will send an ACK after each byte
  5. When done, the master sends a stop condition

Wouldn't this be more efficient?

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Michael gave you the formal response, which is how I2C is defined. The practical problem with your approach is that you fix the register address at 8 bytes. What if a slave

  • has only a single register? Sending 8 address bits would be a waste of time, and a waste of circuitry in the slave.
  • has more than 255 registers?

If you address these issues, you end with a protocol that depends on the type of slave. That would complicate matters considerably.

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  • \$\begingroup\$ What if it has only 1 register? You send the address bits in the first approach aswell? And how does the first approach solve the problem of the 255 registers? \$\endgroup\$ – gilianzz Aug 23 '15 at 14:46
  • \$\begingroup\$ No, with the "current" I2C you don't need the 'dummy write' when the device has only one register (there is no address bit, a one bit address would imply 2 registers), you just do a read. And for > 255 registers a write consists (for instance) of 2 address bytes, followed by the data byte(s). Hence a dummy write is 2 bytes. \$\endgroup\$ – Wouter van Ooijen Aug 23 '15 at 14:53
  • \$\begingroup\$ Well I could delete delete step 3 in my approach if the device only has 1 register and I could send multple register numbers which form the final address. \$\endgroup\$ – gilianzz Aug 23 '15 at 15:04
  • \$\begingroup\$ Yes, but that would yield you a protocol format that depends on the number of address byts (0,1,2,3,...). Imagine designing a bridge chip for that: it would need to know the address format of each (current and future) chip. \$\endgroup\$ – Wouter van Ooijen Aug 23 '15 at 15:06
  • \$\begingroup\$ I see, but when you say "And for > 255 registers a write consists (for instance) of 2 address bytes, ...", wouldn't that yield the same problem? \$\endgroup\$ – gilianzz Aug 23 '15 at 15:10
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It is not done as you propose because once the Slave Address Byte with R/W = 1 for READ is sent the bus is in read mode for data from slave to master. Trying to inject an additional output byte into the sequence with the register address is not a read mode transfer and so the bus mode protocol is broken.

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