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For example take positive edge triggered D flip flop.If input (D) changes from 1 to 0 at the same time when clock pulse goes from 0 to 1(positive edge of clock pulse), what will be the output (Q).Will it be 1 or 0?

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Assume setup time and hold time to be zero

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  • \$\begingroup\$ It will be indeterminate \$\endgroup\$ – Andy aka Aug 24 '15 at 10:26
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    \$\begingroup\$ Depends on the flipflop. What are its setup and hold times? They are in its datasheet. \$\endgroup\$ – Brian Drummond Aug 24 '15 at 10:40
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    \$\begingroup\$ Read up about metastability. \$\endgroup\$ – Dave Tweed Aug 24 '15 at 11:33
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    \$\begingroup\$ "Will it be 1 or 0?" yes. \$\endgroup\$ – Bruce Abbott Aug 25 '15 at 13:51
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Look in the datasheet for the flipflop, and there will be two specs that address this issue: Setup time and hold time. The setup time is how long the input data needs to be held fixed before the clock, and hold time is how long it needs to remain fixed after the clock. If either of these specs is violated, then the answer is you don't know what state the output will settle at.

Some flipflops have either a 0 setup time or 0 hold time. In that case, the input timing you show would work and be valid. In the case of 0 setup time, the output will take on the input value after the clock, and opposite for 0 hold time.

If your data changes within the time window defined by the combination of setup and hold time, then you get garbage out.

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  • \$\begingroup\$ The window shown should really only be used, I would think, on devices which have negative setup or hold times, though for some reason manufacturers seem to specify such times as zero rather than a negative value. Actually, I've often wondered why registers can't two Vih values and two Vil levels, and specify the setup time from when a rising input input crosses the lower Vil, and the hold time from when it crosses the upper Vil, min propagation from when it crosses the lower Vih, and max propagation from when it crosses the upper Vih? That would allow for... \$\endgroup\$ – supercat Aug 26 '15 at 16:13
  • \$\begingroup\$ ...a series of registers to feed each other reliably, even given a somewhat noisy clock, provided that the time between the last device ever seeing the clock below the upper Vil and the first device seeing the clock above the lower Vih exceeded the difference between required hold time and minimum propagation time. \$\endgroup\$ – supercat Aug 26 '15 at 16:15
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Just like @BrianDrummond said. In the datasheet will there be some specifications of how much time the data must be constant before the clock pulse to be accepted as a new value. Here is a video about: Digital Logic - Propagation Delay, Setup, and Hold times https://youtu.be/g8lRqQ-IfYw

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  • \$\begingroup\$ Worth observing that some devices have negative hold times, in which case the question has a definite answer. \$\endgroup\$ – Brian Drummond Aug 24 '15 at 13:04
  • \$\begingroup\$ Some devices with positive hold times may have negative setup times, achievable by adding a delay circuit on the clock input. \$\endgroup\$ – supercat Aug 25 '15 at 14:34
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If the input to the D-flipflop violates the set-up time and arrives too close to rising edge of the clock, the flip flop will either enter a metastable state (and so the output of flip flip will be at an intermediate level for some indeterminate period time ) or will enter a long delay state where the transition at the output of the flipflop is delayed for some confined period of the time (see figure).

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