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I deliberate the datasheet of Atmel's SAM E70 Cortex-M7 and i have a confusion about SPI. When SPI is in master mode, it uses NPCS lines for Chip Select (Slave Select). But i can't find a report which explain that those lines used all of them (as outputs) by the peripheral, or there's able to using one of them. Therefore, it is forced by hardware to make all SPCS lines as outputs in master mode? Or it is possibility to get only one SPCS line, as chip-select, only SPCS0 for example?

By the datasheet:

The SPI operates in Master mode or in Slave mode. The SPI operates in Master mode by writing a 1 to the MSTR bit in the SPI Mode Register (SPI_MR).

  • Pins NPCS0 to NPCS3 are all configured as outputs.
  • The SPCK pin is driven.
  • The MISO line is wired on the receiver input.
  • The MOSI line is driven as an output by the transmitter.
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Being an output or an input has nothing to do with what your lines will do if they are configured as Chip selects.

You may either configure them as GPIOs (in which case they have nothing to do with the SPI subsystem) or as SPCS lines (in which case the GPIO configuration becomes irrelevant). Of course you are able to only configure 1 or 2 or 3 chip selects and the other line(s) as GPIOs (inputs or outputs).

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  • \$\begingroup\$ But according to the datasheet, when SPI works on Master mode, NPCSlines are configured all as outputs. And im considering that if working SPI in Master mode, i will not able to use only one NPCSline as chip-select. \$\endgroup\$ – MrBit Aug 25 '15 at 20:29
  • \$\begingroup\$ You say that i'm able to use only one NPCS line as chip select and the others for, other special function such as GPIO. Right? And why in the datasheet refers: "Pins NPCS0 to NPCS3 are all configured as outputs.", in the master mode description? \$\endgroup\$ – MrBit Aug 25 '15 at 20:32
  • \$\begingroup\$ If you look at the datasheet, p.319 (the graphic) and chapter 30.5.2 you will see that you choose a peripheral function but that is always overriden by the PIO-PE/DR registers (which is basically what tells the pin if it's a GPIO or something else). Sure, the SPI block will drive the signal but the pin will never "see" that signal. \$\endgroup\$ – Tom L. Aug 25 '15 at 20:33
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    \$\begingroup\$ Each NPCS line is routed internally to the PIO controller. The PIO controller decides which function the Pin will actually execute (see the graphic on p.319 where it says Peripheral A Output Enable, Peripheral B output enable, ...). Each pin on that controller can have up to 5 different functions (plus be a normal GPIO pin). Also, think about it: Why is the same NPCS line routed to multiple output pins if all of them were active at the same time? \$\endgroup\$ – Tom L. Aug 26 '15 at 20:07
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    \$\begingroup\$ Chapter 40.6.1:The pins used for interfacing the compliant external devices can be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the SPI pins to their peripheral functions. \$\endgroup\$ – Tom L. Aug 26 '15 at 20:10

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