I started reading about Blocking and Non-bocking assignment with reference to verilog. But when I switched to VHDL its confusing.

What I felt is, in VHDL other than to visually differentiate variable and signal assignment there is no significance for blocking and non-blocking assignment. Am I wrong?


Throw out the terms blocking and non-blocking assignments altogether, they have no place in VHDL. For which I am glad, they seem to cause enough confusion in Verilog.

The one huge advantage VHDL has over not just Verilog but virtually every other digital simulation/verification language out there is its deterministic timing model. In Verilog, simulations may legitimately deliver different results on different simulators because of the order in which processes (tasks, modules) are executed. Can't happen with VHDL - or if it does, there's a bug in the simulator.

But it's worth understanding how this timing model works - I'd say it's absolutely key to understanding VHDL. Grasp this and VHDL will become a lot easier.

It relies on 2 key points:

  1. There are only variable assignments and signal assignments, the latter are also known as postponed assignments.
  2. Time passes in infinitely short slices called "delta cycles" until nothing is happening, when it can step forward some finite timestep (fs, ps, ns) to the next scheduled event (delay, or clock edge).

Variables are local to a process, and variable assignments take place immediately - the next statement sees the new value.

Signal assignments don't happen immediately, but are scheduled to happen after the end of the current delta cycle, when all executing processes have happened. More detail here.

If it still isn't clear, refine the question.


Blocking/Non-blocking is a Verilog thing and at this level, it is best to learn VHDL without doing any association of these items.

If you must, however, variable assignments update immediately, and hence, are a little like blocking assignments. However, variable assignments are always local to a process, and hence, we don't need to worry about that set of race conditions. In addition, variables never have a delay.

Signals update either after a simulation cycle or a specified delay. So perhaps this is a little like Verilog's non-blocking assignment. The delay in VHDL only applies to when the signal is scheduled relative to the current process time and never impacts the process time. Time in a process only advances due to stopping at a sensitivity list or due to a wait statement. And a process never has both a sensitivity list and a wait statement.

Again they are different enough to warrant learning how VHDL's signals and variables work independent of how Verilog's blocking and non-blocking assignments.

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    \$\begingroup\$ "Signals update either after a simulation cycle or a specified delay. So perhaps this is a little like Verilog's blocking assignment" Here u meant Non-blocking right ? \$\endgroup\$ – tollin jose Aug 26 '15 at 12:47
  • \$\begingroup\$ @tollin - Thanks. Yes I meant non-blocking. So my brain twists when I am up too late. \$\endgroup\$ – Jim Lewis Aug 26 '15 at 15:19

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