Throw out the terms blocking and non-blocking assignments altogether, they have no place in VHDL. For which I am glad, they seem to cause enough confusion in Verilog.
The one huge advantage VHDL has over not just Verilog but virtually every other digital simulation/verification language out there is its deterministic timing model. In Verilog, simulations may legitimately deliver different results on different simulators because of the order in which processes (tasks, modules) are executed. Can't happen with VHDL - or if it does, there's a bug in the simulator.
But it's worth understanding how this timing model works - I'd say it's absolutely key to understanding VHDL. Grasp this and VHDL will become a lot easier.
It relies on 2 key points:
- There are only variable assignments and signal assignments, the latter are also known as postponed assignments.
- Time passes in infinitely short slices called
"delta cycles" until nothing is happening, when it can step forward some finite timestep (fs, ps, ns) to the next scheduled event (delay, or clock edge).
Variables are local to a process, and variable assignments take place immediately - the next statement sees the new value.
Signal assignments don't happen immediately, but are scheduled to happen after the end of the current
delta cycle, when all executing processes have happened. More detail here.
If it still isn't clear, refine the question.