I am experiencing fatal errors when synthesising my design with Xilinx XST 14.7 and the
-opt_mode option set to
-opt_mode set to
speed it works fine and synthesis finishes successfully.
The error message I get is the following:
FATAL_ERROR:Xst:xstmacronode.c:118:1.15 - Invalid In Port Name : D from my_port_name, index==-1 Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.
(I replaced the real signal name with
my_port_name for reasons of confidentiality.)
The design never caused problems before (
-opt_mode had been set to speed until now). The error first appeared when switching to
I tried to change the port name given in the error message to something different, but the error still occurs, now complaining about the new port name.
On the Xilinx support forum/answer records are 2 posts with similar topic, but no solution is given (and the version of XST/ISE is a different one).
What (besides a bug in XST) could cause this error?