I am experiencing fatal errors when synthesising my design with Xilinx XST 14.7 and the -opt_mode option set to area. With -opt_mode set to speed it works fine and synthesis finishes successfully.

The error message I get is the following:

FATAL_ERROR:Xst:xstmacronode.c:118:1.15 - Invalid In Port Name : D from my_port_name, index==-1 Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.

(I replaced the real signal name with my_port_name for reasons of confidentiality.)

The design never caused problems before (-opt_mode had been set to speed until now). The error first appeared when switching to -opt_mode area.
I tried to change the port name given in the error message to something different, but the error still occurs, now complaining about the new port name.
On the Xilinx support forum/answer records are 2 posts with similar topic, but no solution is given (and the version of XST/ISE is a different one).
What (besides a bug in XST) could cause this error?

  • \$\begingroup\$ another bug in ISE? More seriously, ISE is fairly well proven so if you find a problem it's likely to be in something unusual, perhaps a weird VHDL construct that ought to work but few people use. Divide and conquer, deleting bits of design until you find the one ... add it here or submit it to Xilinx as a bug report. From the message shown, a negative index might be weird enough to do it... \$\endgroup\$ – Brian Drummond Aug 27 '15 at 11:30
  • \$\begingroup\$ The aflicted module has only ports with constant widhts, therefore I rule this cause out for now. I just noticed that the problem only occurs if I set one of the generics to 2. All other values 1,3,...,10 work fine. The odd thing is, this generic is only used for width definitions of the type <generic>-1. No <generic>-2 or anything suspicious like that. After some try and error and lots of port and signal renaming I found out, that the error does not really refer to a port but to a signal. But still, no out of the ordinary usage of that signal, assigned to once, assigned from twice, that's it. \$\endgroup\$ – andrsmllr Aug 28 '15 at 11:49

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