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Xilinx ISE Design Suite gives information about the resources that a particular design uses. One of the parameters that is given to measure the estimated resources is "Average Fanout of Non-Clock Nets" (as you can see on the botton of the below table where this parameter is 2.5).

I would like to know:

  • Why this parameter is useful
  • How engineers can use or take advantage of this information to improve designs.

Table - Logic utilization - Many rows, last reads average fanout of non-clock nets = 2.5

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    \$\begingroup\$ That's actually a very good question. I'm trying to think of a situation where this figure could be meaningful on its own, but can't find one. It might have had meaning in the early days of FPGAs, and it just stuck around until now. \$\endgroup\$ Aug 30, 2011 at 9:03

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I am no expert on the topic, but my best guess it that it might be used as an input to a power-estimator for the design. The current consumption of each LUT is determined by the clock frequency and the fan-out; by reducing the average fan-out I would assume you could reduce the power-usage. The following article has more on the topic: Power-Aware FPGA Logic Synthesis Using Binary Decision Diagrams

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Fanout is how many inputs a gate output drives. I think knowing the average fanout can give you an idea of how efficiently routed or congested your design may be, and probably how likely to meet your timing constraints. Usually there will be a full report that will also tell you about the nets with high fanout (may report the top 10, or how ever many you ask it to), and logic with maximum delay.

The non-global routes used for normal routing have a much higher delay than global routes (usually used for clock and high fanout nets e.g. reset) so the maximum clock speed will suffer if these nets are very large.
There is usually a setting to limit how large the fanout of a net can be before it gets automatically promoted to a global net, often set to say less than 50. The router will try to automatically duplicate the gate driving the net (or insert a buffer if this is not possible) to avoid exceeding this limit. However if the design is very congested this may not be possible, so a review of the floorplanning or HDL may be in order.
On a related note, it is very important to know about the types of reset your logic can handle. Using the wrong reset or just using reset at all with some blocks, can easily turn a very small design into a large one.
There is a lot more to this can be written about easily here. I would pick up a good book on FPGAs, and/or read the app notes for your FPGA manufacturer who will certainly have plenty written on this subject and more.

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    \$\begingroup\$ Higher fanout means more load, and usually a slower clock rate. I still can't see how the average fanout figure is useful on its own for improving the design (as the OP asked). What could be useful here is a histogram, or at least a max figure. \$\endgroup\$ Aug 30, 2011 at 10:48
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    \$\begingroup\$ I agree somewhat, although I think it could give you a clue to how congested the design is, and maybe some other things. It's just another bit of info you can use to weigh things up - I imagine if you e.g. fiddle with constraints and see the effect on this number (and other alongside it) you will get a "feel" for what it's telling you. \$\endgroup\$
    – Oli Glaser
    Aug 30, 2011 at 11:14
  • \$\begingroup\$ +1 for note on reset. \$\endgroup\$ Aug 30, 2011 at 18:58

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