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I'm looking the datasheet of Atmel's SAM E70 about jtag connection. In my research i was found that to programming the device i need 5 signals:

  • TMS
  • TCK
  • TDI
  • TDO
  • NRST

But i can't find in how provision need to wired. I'm pretty sure that need to be pulled up via 10k-15k resistor, but i'm searching for something official reference.

Atmel not stating something relevant

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Taken from a Segger web page:

1 VTref Input This is the target reference voltage. It is used to check if the target has power, to create the logic-level reference for the input comparators and to control the output logic levels to the target. It is normally fed from Vdd of the target board and must not have a series resistor.

2 Not connected NC This pin is not connected in J-Link. It is reserved for compatibility with other equipment. Connect to Vdd or leave open in target system.

3 nTRST Output JTAG Reset. Output from J-Link to the Reset signal of the target JTAG port. Typically connected to nTRST of the target CPU. This pin is normally pulled HIGH on the target to avoid unin- tentional resets when there is no connection.

5 TDI Output JTAG data input of target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TDI of target CPU.

7 TMS Output JTAG mode set input of target CPU. This pin should be pulled up on the target. Typically connected to TMS of target CPU.

9 TCK Output JTAG clock signal to target CPU. It is recommended that this pin is pulled to a defined state of the target board. Typically connected to TCK of target CPU.

11 RTCK Input Return test clock signal from the target. Some targets must synchronize the JTAG inputs to internal clocks. To assist in meeting this requirement, you can use a returned, and retimed, TCK to dynamically control the TCK rate. J-Link supports adaptive clocking, which waits for TCK changes to be echoed correctly before making further changes. Connect to RTCK if available, otherwise to GND.

13 TDO Input JTAG data output from target CPU. Typically connected to TDO of target CPU.

15 RESET I/O Target CPU reset signal. Typically connected to the RESET pin of the target CPU, which is typically called "nRST", "nRESET" or "RESET".

17 DBGRQ NC This pin is not connected in J-Link. It is reserved for compatibility with other equipment to be used as a debug request signal to the target system. Typically connected to DBGRQ if available, otherwise left open.

19 5V-Target supply Output This pin can be used to supply power to the target hardware.

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  • \$\begingroup\$ This is same on 10pin JTAG? \$\endgroup\$ – MrBit Aug 27 '15 at 17:38
  • \$\begingroup\$ It should be. The signals are identical. \$\endgroup\$ – Leon Heller Aug 27 '15 at 17:50
  • \$\begingroup\$ And this is official jtag connections? Or concern only segger products? \$\endgroup\$ – MrBit Aug 27 '15 at 17:54
  • \$\begingroup\$ I check ATSAMV71-XULT schematic and i see that jtag pins are directly connected in pads (jtag connector) without any resistor. - postimg.org/image/hzlpd5e6f \$\endgroup\$ – MrBit Aug 27 '15 at 18:01
  • \$\begingroup\$ What can i do if a Jtag pin, in my case, TDI, are used for an other peripheral (USART)? \$\endgroup\$ – MrBit Aug 27 '15 at 18:36

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