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Logic gates like AND, OR, NOT etc. often come packed as arrays in ICs. Sometimes not all gates are used in a project. I would like to know how the remaining unused gates should be connected to achieve minimal influence on the system (energy consumption, interference) based on which technology (CMOS, TTL,...) is used.

My application uses a CMOS based hex inverter (CD4069) and the documentation doesnt provide this information.

Note: This is not about several inputs to a single logic gate. In this case connection of the unused pins would be the consequence of keeping the gate functional.

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Like others have already said (I'll just be a little more elaborate), unused CMOS input pins must never be unconnected, because they tend to float towards the dangerous region which is in the middle between VDD and GND. The input pin invariably is connected to another complementary MOS pair's gates, and the process parameters are often optimized for performance so that both the high side and the low side will start conducting a little earlier than in the exact middle point. So in this "middle gray area", both the high side and the low side FETs will conduct some electricity, which results in current consumption, or in some cases, even oscillation if there's a positive feedback path to be found somewhere.

The easiest case and electrically the most stable case is to connect all unused CMOS inputs to ground. But in microcontrollers this can be a little dangerous, because software may make use pins as inputs or outputs. A software update might then make an output from a pin which has previously been unused. In this case, the safest option is to use separate pull-down resistors for each pin. If that is too costly due to the number of resistors and PCB space needed, you can also connect a group of adjacent pins together and pull them low with a single pull-down resistor. In that case, the extra current consumption caused by the surprise software change is usually not that big a problem.

In your specific case of using a hex inverter, there is yet another possibility, which is often used. You can connect the unused inverter inputs and outputs together with some inverter, which is used in the system: connect several inverters in parallel. This is often done to increase the drive capability and thus speed of the inverter, especially when driving large MOSFET gate loads.

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For CMOS, tie the inputs high or low. Do not leave them floating as then they will be in an undefined state and susceptible to external influences and can cause high current consumption or oscillation. It shouldn't make any appreciable difference whether you tie them high or low for a standard logic gate, so long as they are tied somewhere. For TTL, tie them high or leave them floating. Leave the outputs disconnected.

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Usually you want to connect unused logic gate inputs to either VSS or VDD.

In your case, this is exactly what you want to do, and since it's an inverter the choice here doesn't really matter.

The documentation you have does provide this info (figure 17, Page 3-182).

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  • \$\begingroup\$ You are right, somehow I totally missed the description in Fig. 17... \$\endgroup\$ – Grebu Aug 28 '15 at 8:13

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