Level-shifted push-pull gate driver speed problems

Question

I am designing a peak detector with a MOSFET as reset switch. I want to drive the MOSFET by the output of a CD4528 monostable multivibrator (voltage vr in the schematic below). When the N-channel MOSFET Q4 is turned on, the hold capacitor Ch is discharged to -10.5 V through the discharge resistor R (I want my peak detector to work at negative voltages as well within +/- 10 V).

The problem is that I need a gate voltage slightly lower than -10.5 to be sure that the MOSFET is turned of, and a gate voltage higher than about -5 V to be sure that the MOSFET is turned on. The CD4528 is powered with 15 V but does not output negative voltages. I then designed a relatively simple push-pull gate driver with a pnp-based level shifter. The schematic below shows the design:

Since I am using a reset pulse of about 1 microsecond, I found the reset circuit to be too slow, especially at turn-off. Adding a Schottky based baker clamp to Q1 did make it a faster, but still it is too slow.

Any ideas on how to improve the speed of this circuit?

The components used is as follows: Q1 is 2N2907, Q2 is 2N2222, Q3 is 2N2907 and Q4 is the N-channel part of the Si4532 complementary MOSFET pair. D1, D2 and D3 are BAT42. D4 is 1N4148. RB, R1 and R2 are 4.7k. RG and Rd is 1k and Ch is 1n.

By the way: The MOSFET does not like more than +/- 20 V on the gate with respect to the source-terminal, so that is why I want the gate voltage to be within -15 to 0 V instead of +/- 15 V which might be easier to implement.

I have designed a similar reverse polarity peak detector that will detect minimum voltage and is reset by a P-channel MOSFET. In this case I omit the level-shifter and it works fast enough using the same components. So I am sure that it is the PNP-based level shifter that is the problem (SPICE-simulations also confirmed this).

Thanks in advance :-)

Answer 1

Yes, turn-off delay is your big problem. Try

^{simulate this circuit – Schematic created using CircuitLab}

Part (but only part) of your problem is the low current levels you're using, and dropping the resistor values (especially the base resistor) helps speed things up.

Answer 2

I came up with a solution myself. I changed Q1 to a P-channel JFET instead of the PNP. This type of transistor is much faster than the PNP since it does not suffer from slow turn off. It will be turned on when the gate is at 0 V with respect to the source and turned off when gate is at higher voltage than the source terminal.

The only problem is that the JFET has finite on-resistance, so the voltage at the base of Q2 and Q3 will only be at 0 V when RD is infinitely large. This will limit the speed and give problems driving Q2 and Q3. So I will need to choose a low on-resistance P-ch JFET. I tested the circuit with a 2N5462 (the only P-ch JFET I could find in my lab) and with RD = Rb = 4.7k it goes from -15 V to about -1.5 V. This works for me :-)

Answer 3

One common approach in circuits like this is to put a speed-up capacitor across Rb to remove the charge when turning off the transistor - something like 100pF would be a starting point.

R2 also looks to be a bit high - you could try reducing those to speed up the transition of that node.