I am working with a 74HC193 binary up/down counter, and am trying to set up a button to increment or decrement it. The procedure to increment a single step as I understand it is:

  1. Set pin 4 high
  2. Wait for change to propagate (30ns or more)
  3. Set Pin 5 high
  4. Wait again
  5. Set both pins low again.

Since it is a button, I am not worried about speed in any way. I would be perfectly happy to have a 2ms pulse followed by a 1ms pulse 1ms later. In my research online, the most promising way to make a pulse is a monostable 555 circuit. I was thinking two of those wth different T values might work, but I can't tell from that page if I can put it on a delay. That seems like a fairly decent debouncing mechanism as well, but I would like a little more control, like a 2ms pulse but 500ms before another input is accepted. Is that possible?

If it is too hard to get two pulses with the proper timing, I suppose I could just hold the count down line high and pulse the count up line once, but that removes my ability to have an additional button to count down.


I think you are making things more difficult for yourself than they really are. The procedure for a count up is:

  • CPU and CPD are high (system in rest)
  • CPU is make low
  • wait some minmum time
  • CPU is made high again (system in rest)

I don't fully understand what you mean with "and am trying to set up a button to increment or decrement it": one button to count up, another to count down? That is easy, just debounce the buttons (a pair of 555, or one 556, would do), and feed the signal (must be high in rest!) to the CPU and CPD inputs.

If you want to have a button that selects the function (up or down) of a count button the circuit is a little bit more complex. I think there are other counter chips that have a select and clock input insetad of two clock inputs, which would be easier in this case.

  • \$\begingroup\$ I do indeed mean two separate buttons. \$\endgroup\$ – captncraig Aug 30 '11 at 17:32
  • \$\begingroup\$ The datasheet says: "Only one clock input can be held HIGH at any time, or erroneous operation will result." I assumed this meant that both clocks low was the safest "rest" state \$\endgroup\$ – captncraig Aug 30 '11 at 17:33
  • \$\begingroup\$ If it is safe to rest them high, that will simplify quite a bit. I use the parralel load feature, but not the clear. \$\endgroup\$ – captncraig Aug 30 '11 at 17:37
  • \$\begingroup\$ Indeed it says so, but I can't make sense of it. The text immediately before its clearly talks about pulsing one clock while holding the other high, which implies both being high at some point. The diagram at page 7 clearly shows the high/high input a the 'idle' situation. So I assume the scentence you quote is an error, maybe it should be "only one clock input can be held LOW", that would make sense. \$\endgroup\$ – Wouter van Ooijen Aug 30 '11 at 18:45

I deleted my other answer because I overlooked an important point in the part's truth table, which you correctly pointed out: while both count-up (pin 5) and count-down (pin 4) are low-to-high edge-triggered, the edge is ignored if the other count input is low.

We'll suppose you have a decently debounced positive pulse, for instance obtained from the 555 debounce circuit you're referring to. Apply that pulse directly to pin 4 (count-down) and delayed by a short time to pin 5 (count-up). The delay can be created by a couple of gates. Then both inputs will see a rising edge, but for the count-down pin this will be while the count-up is still low, so it won't have any effect. The rising edge for the count-up input will occur while the count-down input is already high, so this will have an effect.

So all you have to do is put pulse directly to the count-down input, and the delayed pulse to the count-up input.

  • \$\begingroup\$ I like that idea. It keeps me only needing 1 555. I am thinking I'll just snake the signal through a hex inverter. At 8ns propagation per gate that gives me 64ns delay, which is more than safe. \$\endgroup\$ – captncraig Aug 30 '11 at 17:04
  • \$\begingroup\$ The 555 is a bit of overkill though isn't it. A simple RC circuit should be fine shouldn't it? \$\endgroup\$ – captncraig Aug 30 '11 at 17:11
  • 1
    \$\begingroup\$ @CMP - Hex will give you 48ns of course :-). But that's safe as well, because the setup time for the HC193 is in the order of 1 gate delay. Just make sure you use an even number of gates. You can also use gates from the CD4000 series, those are pretty slow. \$\endgroup\$ – stevenvh Aug 30 '11 at 17:14
  • \$\begingroup\$ @CMP - If you only ever want to count one way I think you could just tie the other count pin high. \$\endgroup\$ – Oli Glaser Aug 30 '11 at 17:14
  • \$\begingroup\$ @CMP - Yes, an RC will do. \$\endgroup\$ – stevenvh Aug 30 '11 at 17:15

It's not totally clear exactly what you are trying to do, but it seems the basic problem is to make a counter increment and decrement based on user button presses. You also want additional features, like ignore new activity within some window of a button event.

This is really crying out for a microcontroller. It can do the button debouncing, increment/decrement a counter of essentially any width, and perform the time-based lockout functions, all in the single part. Even the smallest micro will have way more processing power than required for this, so the issue is just I/O pins. You apparently want 4 counter bits with parallel output, and you seem to have two button inputs. That's a total of 6 I/O pins, so even a 8 pin micro is possibly good enough if you get one that can run from a internal oscillator. Any PIC 12F with a internal oscillator should be able to do this job easily. Some parts have internal passive pullups, which would allow you to connect the buttons without any additional parts.


I should have mentioned that when debouncing a user input, a 30-50 ms timeout is usually good. Even 50 ms will feel instantaneous to the user, and most switches stop bouncing after 10 ms, although some aren't so good. I usually use 50 ms unless there is a reason not to. I've seen some really cheap switches bounce as long as 30 ms when not pressed extra firmly. I'm not sure what exactly the 2 ms and 3 ms times are supposed to be in your description, but if those are meant to be debounce times then they are too short unless you have some very special switches. Again, up to 50 ms (1/20 second) feels instantaneous to users, so there is little advantage in a shorter debounce time.

  • \$\begingroup\$ I don't think steven asked for a particular problem to be solved. His problem seems to be a misunderstanding of the datasheet (which is, I must say, at the very least misleading). \$\endgroup\$ – Wouter van Ooijen Aug 30 '11 at 18:47
  • \$\begingroup\$ @Wouter: You could be right. It's not clear what exactly he's asking so I answered it as "I'm confused about buttons, counters, and debouncing". A better answer will require a better question. \$\endgroup\$ – Olin Lathrop Aug 30 '11 at 18:50
  • \$\begingroup\$ I intended that to be the pulse width after the debounce time. The actual values are insignificant. \$\endgroup\$ – captncraig Aug 30 '11 at 19:18
  • 1
    \$\begingroup\$ @Wouter: I don't normally follow links in questions unless the issue is specifically about datasheet parameters, which this didn't seem to be. However, I just took a look and I agree. Both count inputs high would be the normal idle state. When in doubt with 74xxx logic, refer to the TI databook. My version from 1976 clearly shows both count inputs being high when no counting is going on. \$\endgroup\$ – Olin Lathrop Aug 30 '11 at 20:37
  • 1
    \$\begingroup\$ Well, if the three of US agree it must be true :) \$\endgroup\$ – Wouter van Ooijen Aug 30 '11 at 21:16

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.