I'm new to EMIF (external memory interfaces) and I ran into kind of a dumb question about DDR3- not super important but mostly me just wondering if there's an answer I'm not thinking of. Basically I'm wondering- if you need to send 12 bits for both the row and column addresses, why is there only one 12 bit address bus?
Is it because the row address needs to arrive first (side question, does it need to arrive first or is that just convention)? Or is it a due to physical constraints of the number of pins?
Any help or documentation or references would be really appreciated. Thanks!