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I'm new to EMIF (external memory interfaces) and I ran into kind of a dumb question about DDR3- not super important but mostly me just wondering if there's an answer I'm not thinking of. Basically I'm wondering- if you need to send 12 bits for both the row and column addresses, why is there only one 12 bit address bus?

Is it because the row address needs to arrive first (side question, does it need to arrive first or is that just convention)? Or is it a due to physical constraints of the number of pins?

Any help or documentation or references would be really appreciated. Thanks!

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  • \$\begingroup\$ Are you are taking about Synchronous-DRAM or asynchronous-DRAM?, did you mean 13 bit?because SDRAM has Banks? \$\endgroup\$ – MaMba Aug 29 '15 at 19:08
  • \$\begingroup\$ @MaMba: There's no such thing as asynchronous DDR DRAM. DDR (double data rate) always implies a synchronous interface. \$\endgroup\$ – Dave Tweed Aug 29 '15 at 20:09
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Generically speaking, DRAM — whether asynchronous or synchronous, SDR or DDR — receives the row addresses and column addresses multiplexed on a single set of pins.

With older asynchronous DRAM, this is controlled explicitly by the RAS (row address strobe) and CAS (column address strobe) control pins.

With synchronous DRAM of any type, the RAS, CAS and WE pins have been combined into a more generic command bus, but the basic concept is still the same: row addresses and column addresses are transferred on two separate clock cycles.

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You need to look at exactly what DDR3 device part number you want to use. Then get ahold of the manufacturers data sheet for that part to understand specifics about that part. Then, as is the case with most manufacturers, you need to get the family data sheet for that part. This latter document will provide you with the answers to all your questions and a whole lot more that you will need to deal with to get a memory controller interface implemented.

We cannot help you locate these materials because you have provided no part type information.

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  • \$\begingroup\$ This answer is not particularly helpful. There are generic things that you can say about DRAM interfaces without knowing a specific part number, and these would answer the OP's questions. \$\endgroup\$ – Dave Tweed Aug 29 '15 at 20:16
  • \$\begingroup\$ @DaveTweed - Not so sir. Size of address bus for just one item of question varies by part number. \$\endgroup\$ – Michael Karas Aug 29 '15 at 20:42
  • \$\begingroup\$ And besides all that if anyone wanted to design a memory controller to talk to DDR3 RAM or deploy RAMs connected to some computer chip that already came with a controller on board they better get the documentation that I described. \$\endgroup\$ – Michael Karas Aug 29 '15 at 20:46
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The Row / Column addressing of DDR3 DRAM was already used on DDR2, SDRAM, and even asynchronous DRAMs more than 30 years ago.

It is related to the way DRAMs are organised.

The single transistor/capacitor used for storing each bit cannot be directly addressed like in a static memory. Whole rows are copied to and from a temporary buffer before allowing column accesses (actually positions inside the buffer), or for refreshing a whole row.

As row and column addresses cannot be used simultaneously, there is no need for separate pins.

(Besides, of course, ask Wikipedia...)

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