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My project is to extract a gate level netlist from layout, I am going write a parser for GDSII file format.

However, I have trouble in relating the record information represented in the GDSII format specification to the topology of the whole design or even a single gate.

Here is a very useful SPEC of GDSII file format: http://www.rulabinsky.com/cavd/text/chapc.html

I can get the position of polygon, wire, and cell, however I have no idea how to detect a MOSFET, which can be used to determine a corresponding logic gate.

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    \$\begingroup\$ And your question is .... ? \$\endgroup\$ – Dave Tweed Aug 29 '15 at 23:51
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As you parse the data for the individual layers, you need to re-create the 3-D geometry that they describe. You need to figure out how individual polygons within a layer connect to each other to create larger structures, you need to discover where vias create connections between layers, and you need to recognize the places where gates and diffusion work together to create transistors.

A very long time ago, I wrote a similar program to extract a netlist from a set of PCB Gerber files, which is a similar low-level description of the geometry. It is not a trivial task, because you basically need to compare every vertex with every other vertex. I optimized the process by first sorting the vertices into a 2D array of "bins" and then doing a much smaller exhaustive comparison among the vertices within each bin (and its neighbors).

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