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I tried to draw the a CMOS logic circuit, but I don't know whether is is right or not.

The function is: \$ F = \overline{A} + B \$

$$ F = \overline{A} + B $$

$$ \overline{F} = \overline{\overline{A} + B} \Rightarrow A \times \overline{B} $$


enter image description here


schematic

simulate this circuit – Schematic created using CircuitLab

Link to original paper.

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  • \$\begingroup\$ The expression is \$(¬A)+B\$ or \$¬(A+B)\$? \$\endgroup\$ – Cehhiro Aug 31 '15 at 16:21
  • \$\begingroup\$ Its (~A)+B.@OFRBG \$\endgroup\$ – Res Aug 31 '15 at 16:26
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Here's your circuit:

schematic

simulate this circuit – Schematic created using CircuitLab

Please note that since the high side mos are P mosfets they are on when the input is low.

How did I draw that? First of all you need to fill the truth table, then you build the pull down network, i.e. the NMOS part, and the pull up network separately.

Let's make the table:

A    B    F
0    0    1
0    1    1
1    0    0
1    1    1

Inspecting the table you can see that the output is low when A=1 and B=0. Your pull down network will consist of two series (logical AND) transistors, one connected to A, the other to /B.

The output is high if A=0 or (A=1 and B=1). Note that here I have already simplified the formula (search for karnaugh maps, minterms, maxterms, product of sum, sum of product).

Your pull up network will consist of the parallel (logical OR) of:

  • the series (AND) of two transistors, one connected to /A, the other to /B
  • a single transistor connected to A

Note that i inverted the signals for the pull up network because P mos turn on when input is LOW.

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  • \$\begingroup\$ sry i didn't understand the PMOS part.@Vladimir Cravero \$\endgroup\$ – Res Aug 31 '15 at 17:09
  • \$\begingroup\$ Yeah... What about it exactly? \$\endgroup\$ – Vladimir Cravero Aug 31 '15 at 17:10
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    \$\begingroup\$ M5 is not really necessary, since the expression "A=0 or (A=1 and B=1)" is logically equivalent to "A=0 or B=1". \$\endgroup\$ – Reinstate Monica Aug 31 '15 at 18:09
  • \$\begingroup\$ You have used three input on the PMOS side and two on NMOS side, but as much as i have studied CMOS you are required to have same number of inputs on both PMOS and NMOS side. \$\endgroup\$ – Abhishek Tyagi Aug 31 '15 at 18:23
  • \$\begingroup\$ @AbhishekTyagi can you provide any source on this? CMOS stands for 'complementary MOS' and I do not see equal number of inputs a requirement. Think of a function that must be low when one input is high, and high when any other input is low, i.e. something like A(/B+/C+/D...). This can be implemented with one transistor on the PDN and all the others on the PUN. \$\endgroup\$ – Vladimir Cravero Aug 31 '15 at 20:33
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Its a tricky question and this must have been told to you by your tutor. I am giving away the answer here since because you have tried it. The truth table for this

enter image description here

You can see from the table that for the case A=T and B=T output is T and for A=T and B=F output is F. The transition in the value of B from T to F indicates that one of the inputs has gone low, so CMOS being a negative logic the output should either remain the same or or show a F to T transition.

In this case, F to T transition is not applicable since initial output is T , so for this circuit to be implementable with CMOS, the putput should have remained T. Hence this function can not be realized with a SINGLE CMOS CIRCUIT

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  • \$\begingroup\$ Thankyou...but please upload the logic circuit for this...@Abhishek Tyagi \$\endgroup\$ – Res Aug 31 '15 at 16:55
  • \$\begingroup\$ Abhi, I believe our definitions of CMOS circuit are quite different. \$\endgroup\$ – Vladimir Cravero Aug 31 '15 at 17:07
  • \$\begingroup\$ @VladimirCravero How come, can you please elaborate? \$\endgroup\$ – Abhishek Tyagi Aug 31 '15 at 18:20
  • \$\begingroup\$ You say that such a circuit can't be built but I've built it just above your answer... \$\endgroup\$ – Vladimir Cravero Aug 31 '15 at 18:23

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