I'm looking for succinct yet correct guidelines for evaluating a DDR3 memory PCB layout. I know that trace length matching, via style and back-drilling, and signal grouping all matter. I know that each group of 8 data bits plus two associated control lines need to be length matched.

I'm seeking a good summary of all the issues, or people's experience, especially if it covers both multi-chip modules and single point to point (one CPU and one memory chip) layout. How critical is all this stuff for small single board CPU's?

I have read DDR1 Layout Considerations - DOs and DONTs and Compensating for unbalanced via count in DDR3 routing

  • \$\begingroup\$ www.micron.com used to be a good place to look for Technical Notes covering this information. They've deleted some useful stuff but it maybe still is if you can navigate it. \$\endgroup\$
    – user16324
    Commented Sep 1, 2015 at 22:05
  • \$\begingroup\$ Yeah, I've read Micron TN-41-13 "DDR3 Point to Point Design Support" a half dozen times without a lot of lightbulbs going off. Thus my question here. \$\endgroup\$
    – Bryce
    Commented Sep 3, 2015 at 19:19
  • \$\begingroup\$ DDR3 is significantly easier to lay out than its predecessors. When I get to a real keyboard I will ecpound, assuming someone else has not already done so. \$\endgroup\$ Commented Oct 17, 2015 at 20:01

1 Answer 1


In a pair of an MPU and a DDR3 --- it is mostly covered by the considerations listed for the MPU --- generally, in its datasheet and/or related documentation.

For example, take a look on AM437x (see doc, sec., there are many variants (single chip, multiple chip, DDR type, etc) considered and covered by related rules.

You may be surprised but the sufficient set of rules necessary to trace DDR3 memory is frequently (if not always) dictated by the MCU/MPU you select and not by the memory you connect to --- and there is no something strange there because exactly the MCU dictates the parameters (clock freq, bus width, addressable volume, timings and modes, etc) it will (can) interact with the memory, since the MCU is the bus master.

  • \$\begingroup\$ how does one ensure that the via has 50 ohm impedance, is that possible or required? \$\endgroup\$
    – quantum231
    Commented Apr 25, 2023 at 9:09

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