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Some of you may remember that I posted a question where I requested some feedback on my PCB design. The design was for a Half-Bridge driven by a IR2113 chip. I went ahead and etched the PCB but unfortunately, only the low side MOSFET seems to switch. In my initial calculation, the bootstrap capacitor's value came out to be 1uF or so. Initially, since the circuit didn't work, I decided to change the capacitor to a higher value (100uF).

That didn't cause any change in the circuit. However, if I short out the capacitor the High-Side does turn on. The gate voltage is around 11V. If I don't short out the capacitor, the gate voltage is around 5.5V.

The low side seems to switch just fine. There is a bit more weirdness to the circuit: the SD pin is supposed to low in order to enable the chip - yet, having it high makes no difference to the output. I am still able to switch the Low-Side MOSFET. Furthermore, it seems that somehow the Lin and Hin pins are switched. If I connect the Lin pin to High, it doesn't switch on/off the Low-Side. Infact, if I take the Hin pin and take it High, it causes Lo output to turn on the Low-Side.

The following is my circuit. C2 is 0.1uF and C1 (bootstrap) was 1uF (as per calc.) but I've changed it to a larger value (100uF) incase I was wrong somewhere. For the load, I have a 1K resistor connected. Vcc is 12V.

Previous Schematic: http://i.stack.imgur.com/T3fRn.png

I have updated the schematic. I hope it looks better now. if there if still some confusion, please let me know. I sincerely apologize for wasting the time of folks here. I understand that the schematic was hard to follow. I drew it in haste and I was also not familiar with ERC and DRC checks and I've just started to read up on them.

Getting back on topic: the PCB layout hasn't changed so I'm not sure if if I should just etch another PCB altogether or not. One of my main concerns is that in the datasheet, the source of the upper MOSFET and the drain of the lower MOSFET are not connected. Instead, they are connected to the load. However, in the various schematics I've seen online (case in point), they are connected. Would this make any difference?

Also note that the datasheet has two bypass caps. One is connected between Vcc and Gnd. The other is connected between Vdd and Vss. In my case, the Vdd is tied to Vcc therefore I'm only using one bypass cap.

I again apologize for the poorly drawn schematic that I posted previously.

enter image description here

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  • \$\begingroup\$ Schematic shows IC1 as 4561N but text says IR2113; which is it? \$\endgroup\$ – Mike DeSimone Aug 31 '11 at 14:51
  • \$\begingroup\$ Its IR2113. I'm using the footprint of a 14pin DIP, hence the label on the schematic. \$\endgroup\$ – Saad Aug 31 '11 at 14:52
  • \$\begingroup\$ @saad - Thanks for cleaning up the schematic, it looks much better now. Did you build your PCB based on the old schematic (which had both material and stylistic errors), or build it on protoboard based on your intent for the schematic (as reflected in the current revision)? \$\endgroup\$ – Kevin Vermeer Aug 31 '11 at 16:10
  • \$\begingroup\$ Kevin, I built the PCB based on the previous schematic. It seems that I should just trash the PCB and etch another one based on this, revised, schematic. \$\endgroup\$ – Saad Aug 31 '11 at 16:13
  • \$\begingroup\$ If your test load is a 1k resistor, then LED2 + R4 is a more significant load: there will be a drop across LED2 (just below 2 V for red, just above for yellow-green, and around 3.5 V for true green, blue, or white) and the rest of the voltage is across R4. Assuming a red LED of 2.0 V drop, current will be 25 mA, which is really close to the limit for standard LEDs (2.0 mA is much more sane for a simple indicator). Compare this with 12 mA in the 1k resistor. This means 1/4 W will be dissipated in R4 and 50 mW in LED2; check the datasheets to see if this is okay. Same for LED1 and R3. \$\endgroup\$ – Mike DeSimone Aug 31 '11 at 17:48
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There are a number of uncertainties in what you say you are doing. You need to stabilize the patient and understand what is really going on in order to make progress. At present there are several things wrong which are obscuring each other. Being able to deal with each ne in isolation makes life much easier.

(1) Your sentence below does not make sense. Can you please explain more clearly what you mean. "The MOSFETS are connected" and "drain and source ... connected" can both mean the same thing. If they DON'T mean the same you need to explain what you mean. You said:

  • " My main concern is that in the datasheet schematic, The mosfets are connected. Whereas in my circuit (and others that I've seen over the web), the drain and source are connected together."

(2) This would be fatal:

  • My Vdd is the same as Vss, and so I'm using the same cap. for both of them - assuming thats ok.

As Oli says, presumably you mean Vdd = Vcc. You need to read what you write before sending. We all need to and we all get it wrong sometimes BUT when you are asking the questions and want help then confusing the assembled masses with typos is a very bad idea.

(3) This probably means that your IC is dead or walking wounded OR you have a disconnected line - possibly ground. When things go this wrong you need to carefully measure everything - voltages when on and ohmic connections when off. look for shorts AND opens.

  • ... the SD pin is supposed to low in order to enable the chip - yet, having it high makes no difference to the output. I am still able to switch the Low-Side MOSFET. Furthermore, it seems that somehow the Lin and Hin pins are switched. If I connect the Lin pin to High, it doesn't switch on/off the Low-Side. Infact, if I take the Hin pin and take it High, it causes Lo output to turn on the Low-Side.

(4) If you were using "real" voltages your IC and random other things would now be dead. Shorting the capacitor connects the isolated high voltage "island" in thje IC to the drain of the lower FET which gets connected to ground when the lower FET is turned on. Shorting this cap could be an extremely exciting and non productive thing to do in many situations. Hopefully you determined before you did this what you expected to happen and didn't just do it to see what happened. When you are dealing with power rather than signal the magic smoke is never too far away. You may have had some already without being aware of it.

  • That didn't cause any change in the circuit. However, if I short out the capacitor the High-Side does turn on. The gate voltage is around 11V. If I don't short out the capacitor, the gate voltage is around 5.5V.

(5) Making the capacitor 100 times larger than you calculate in a circuit that may be switching at 10's to 100's of kHz is highly likely to produce interesting results. These could include an interesting emulation of lot's wife. But may not. The capacitor has to charge in the time that the low side FET is on. It discharges when the high side FET turns on. There will be charge & discharge time constants controlled by the resistance in the IC power paths. This may still work OK OR the voltages may only rise to a fraction of what is intended in the time available. Which may be consistent with what you are seeing.

I could add a bit more but that should do to start :-). Sometimes we all have a bad day - you need to try and not let too many things at once get out of control as then you can't asily analyse what is going wrong.

As others (and I) have suggested, measure everything you can and see if it makes sense. If you have an oscilloscope see what it can tell you. If you don't have a'scope, start putting lunch money aside for one. Even a relatively cheap scope can be a mightily powerful tool. An oscilloscope is possibly the most effective and powerful debugging and fault finding aid you will ever have for analog circuits.

  • In my initial calculation, the bootstrap capacitor's value came out to be 1uF or so. Initially, since the circuit didn't work, I decided to change the capacitor to a higher value (100uF).

Practical aspects:

If hand driving at low speed, connect Hin and Lin and SD low with pull down resistors. Then, if you hand switch them and they "bounce" they will bounce from low to applied signal level and not to some unknown state.

BUT the bootstrap powering circuit for the upper gate completely relies on there being an AC signal at VS to supply AC at Vb which draws power from Vcc and delivers it to Vb. If there is no AC your =upper gate signal will decay "rapidly". How long it takes depends on upper driver power consumption and was part of your capacitor calculations (from memory). This is an example of where an oscilloscope will help you see what is happening. The 100 uF you are using is a large value and decay time may be long enough to see what is happening "by eye", but maybe not.

If you want to drive with a microcontroller you could reduce Vcc to Vdd rather than raising Vcc - as long as IC minimum voltage spec is still met.

Re-etch of PCB MAY be a good idea BUT you should be able to carefully go over circuit and check that what you have is what you intend. Do it pin by pin.Talking to yourself about it as you go can help :-) (really). Describe what you expect to see and what you really see and why they are or aren't compatible. [Watch for men in white coats observing you suspiciously when you are talking to yourself - or do it in your head or, works well, get a knowledgeable friend and explain it to them. The very act of explaining often works wonders.]

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  • \$\begingroup\$ Thank you for taking the time out to write this. I have updated my question and I hope its now clearer. I understand its possible that I've already fried the circuit. I should probably think about etching another PCB for this. I apologize for the text not being clear - English is not my main language and I sometimes have difficulty describing things. Usually a picture describes this sort of thing perfectly, but my schematic was poorly drawn. What I meant was: the the source of the upper MOSFET is connected to the drain of the lower MOSFET. Is this an issue? \$\endgroup\$ – Saad Aug 31 '11 at 15:51
  • \$\begingroup\$ One more thing: I am currently not using a PWM input to Lin and Hin. Instead, I connect them by hand to +12V or 0V. This was probably another of my boneheaded ideas, but I thought I should mention it too. I suppose that this will probably not work? I did this in order to keep things simple. But if this is not a good way to test the circuit, I'll input a PWM waveform using my AVR - though I will need to change Vdd. Instead of connecting it to 12V, I will need to connect it to 5V. (is my understanding correct regarding this?) \$\endgroup\$ – Saad Aug 31 '11 at 16:11
  • \$\begingroup\$ @saad - See addition "Practical aspects" at end of my answer. (Adding now) \$\endgroup\$ – Russell McMahon Aug 31 '11 at 20:19
  • \$\begingroup\$ "The 100 uF you are using is a large value and decay time may be long enough to see what is happening "by eye", but maybe not." Corrolary: After a falling edge, HIN must stay low long enough to recharge the capacitor. If 100 uF keeps the FET on for a second, the FET must stay off for at least a second to recharge. \$\endgroup\$ – Mike DeSimone Sep 1 '11 at 2:59
  • \$\begingroup\$ Longer times will be needed to charge and discharge as cap increases, but they need not be equal and probably will be far from equal. \$\endgroup\$ – Russell McMahon Sep 1 '11 at 4:31
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This is a great example why neatness and attention to detail matter. Sloppiness like drawing nets right thru other parts leads to mistakes or at least makes it less likely mistakes will be noticed (because it already looks like a mistake so the brain tunes out the real ones).

Look carefully at the schematic. Note that the anode of the diode and one side of C1 do not have a dot showing that the software thinks there are connections there. Maybe it does, but then the schematic is misleading. If the software (looks like Eagle?) doesn't think those nets are connected, then they won't be connected on the board. Both those parts create the power supply for the high side drive, so these issues match your symptoms.

Once again folks: Neatness and attention to detail matter!

This should be self-evident, but apparently there are a lot of sloppy people out there. There is no place and no excuse for this in engineering. This schematic is sloppy in various places. I would never dream of letting a customer or anyone else see a schematic from me that looked like this. I would be embarassed to let anyone see this, and you should be too. The fact that you're not says a lot about you. Doing it right is really quite easy and hardly takes any time. Just avoiding one such error makes it worth while. How long have you spent diagnosing the problem and will spend fixing it, compared to maybe 5 minutes to clean up the schematic and run the ERC and DRC checks? Don't draw nets thru or right up against parts, if you rotate a part fix the text so that it is normally readable again, make sure the text doesn't collide with other things, etc. Again, this should all be self-evident. Hopefully you have learned a lesson here and will be more careful in the future.

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  • \$\begingroup\$ I've made sure that Vs and the bootstrap capacitor are connected. Similarly, the diode between Vb and Vs is also connected properly. Not that it excuses the sloppiness, just putting it out there capacitor and diode connection isn't the issue. \$\endgroup\$ – Saad Aug 31 '11 at 14:35
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As Olin mentions, the schematic looks like it has a few (unintentional most likely) mistakes that will be propagated through to the PCB. Looks like there may be a (according to datasheet diagram) bypass cap missing too.
I wouldn't worry too much if this is the first attempt at doing this stuff, and it's a personal project.
Take care with drawing the schematic, learn about and get into running ERC/DRC checks regularly, and these kind of mistakes become a lot harder to make.

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  • \$\begingroup\$ Thanks. I assume you mean the cap. between Vdd and Vss? My Vdd is the same as Vss, and so I'm using the same cap. for both of them - assuming thats ok. My main concern is that in the datasheet schematic, The mosfets are connected. Whereas in my circuit (and others that I've seen over the web), the drain and source are connected together. Do you think this will cause problems? \$\endgroup\$ – Saad Aug 31 '11 at 14:47
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    \$\begingroup\$ This is getting confusing :-) Do you mean the upper mosfets source is connected to the lowers drain as in your schematic? Also could you give us the intended (and preferably measured) voltages for Vdd, Vcc and Vss? \$\endgroup\$ – Oli Glaser Aug 31 '11 at 14:57
  • \$\begingroup\$ Your Vdd should not be the same as Vss. Did you mean Vdd same as Vcc? \$\endgroup\$ – Oli Glaser Aug 31 '11 at 15:06
  • \$\begingroup\$ @Oli: That's a typical connection for a N-channel-only half-bridge. Diode D1 and capacitor C1 keep the VB node at VC + VS so long as Q1 isn't switched on for too long. (The length of time that Q1 is on determines the size needed for C1. 1.0 uF is a typical value. Also, D1 needs to be an ultrafast recovery or Schottky diode.) \$\endgroup\$ – Mike DeSimone Aug 31 '11 at 15:28
  • \$\begingroup\$ @Mike - yes, I was just checking whether he didn't mean the individual mosfet source and drains were connected. \$\endgroup\$ – Oli Glaser Aug 31 '11 at 15:37
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  1. Substituting a 100 uF capacitor for a 1 uF capacitor is not valid at higher frequencies because the ESR and ESL of a tantalum or electrolytic capacitor come into play and become dominant at higher frequencies.

  2. Stray inductance caused by layout can cause problems. Make sure these loops enclose a minimum of area:

    • IC1 VB to C1 and back to IC1 VS
    • IC1 HO to R1 to Q1 gate, and Q1 source back to IC1 VS
    • IC1 LO to R2 to Q2 gate, and Q2 source back to IC1 COM
    • HIN driver OUT to X3 pin 1 to IC1 HIN, and IC1 VSS back to HIN driver GND. Yes, you probably need to route a ground line with the signal; expecting GND to magically stay at 0 V via X1 pin 2 is probably not enough
    • LIN driver OUT to X3 pin 1 to IC1 HIN, and IC1 VSS back to HIN driver GND.
  3. Check VIH and VIL for IC1 HIN and make sure you're driving the right levels.

  4. VC (Q1 drain) doesn't seem to be hooked up to a power supply.

  5. Also, the 1N400x series diode might be too slow for the application. Try a Schottky or ultra-fast diode.

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