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Floorplanning is the step, in which functional blocks are allocated on chip area and total chip area, pins location are finalized.

Now what is the difference in Floorplanning for FPGA, ASIC and Gate Arrays?

I believe, FPGA & Gate Array both do not require floorplanning.

Kindly comment on my view.

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  • \$\begingroup\$ Can you explain why you believe that FPGA and Gate Array do not require floorplanning but an ASIC does ??? \$\endgroup\$
    – Bimpelrekkie
    Commented Sep 1, 2015 at 12:54
  • \$\begingroup\$ Do you mean a floor plan or layout? Layout is not required for FPGAs and GAs. \$\endgroup\$
    – judoka_acl
    Commented Sep 1, 2015 at 13:14
  • \$\begingroup\$ @FakeMoustache : Because floorplanning is about tentative placement of large functional blocks on Silicon Surface and layout is already developed for FPGA & Gate Array. \$\endgroup\$
    – Karan Shah
    Commented Sep 1, 2015 at 15:47
  • \$\begingroup\$ Floor planning is the very basic design parameter that cant be skipped, it discusses the various influences of localization of parameters/blocks on the model, For ex. placement of a module very far away may cause undesirable effects on the micro-strip lines, a perfect floor plan help minimize this. \$\endgroup\$
    – MaMba
    Commented Sep 1, 2015 at 17:25

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Well the difference is that FPGAs and Gate Arrays do have already existing physical design. In some cases you don't bother to do floorplan for FPGAs.

Imagine that you need to use a RAM in your design. Most of the FPGAs have their dedicated SRAM, so you can assign your RAM to it or just use many cells to do the same job.

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  • \$\begingroup\$ But since layout is already developed for both FPGA & Gate Array and floor planning is tentative placement on Silicon surface, how is it possible in FPGA or Gate Array? \$\endgroup\$
    – Karan Shah
    Commented Sep 1, 2015 at 15:48

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