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For example:

It is said to accept more than 1 kV between its collector and emitter. It comes in a SOT-223 package (3 pins plus a tab). With a dielectric strength of 1 kV/mm for humid air, cannot an arc appear between the electrodes?

Or do you have to enclose the package in glue or other material with higher dielectric strength than air?

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  • \$\begingroup\$ How can they put a 150A MOSFET die in a 78A package? "Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 78A" \$\endgroup\$ – Spehro Pefhany Sep 1 '15 at 15:51
  • \$\begingroup\$ @Spehro Pefhany where did you see those 150A? That chip has a 400mA max current and that's the "Collector peak current (tP < 5 ms)". \$\endgroup\$ – Fizz Sep 1 '15 at 19:58
  • \$\begingroup\$ @RespawnedFluff A different part! (power MOSFET) Just a reminder that the package may limit what the chip is capable of. \$\endgroup\$ – Spehro Pefhany Sep 1 '15 at 22:30
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    \$\begingroup\$ @Spehro Pefhany: Ah, a bit of googling found that you're talking about IRLB8743PbF. \$\endgroup\$ – Fizz Sep 1 '15 at 23:00
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Hmm, it does seem tight. The pin pitch is 2.3 mm, and the maximum pin width is .85 mm, leaving 1.45 mm minimum space between pins. The transistor is specified for 1.4 kV C-E, which are on adjacent pins, so that's just about 1 kV/mm. As I said, that seems tight, and you'd have to be careful in designing the PCB footprint to not make this worse.

Usually I make PCB pads a little wider than the pins, but in this case I wouldn't. Even if you make the pads the same width as the pins, then any alignment error cuts into the spacing.

Overall, I'd prefer a larger package with more space between pins to get somewhat below 1 kV/mm.

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  • \$\begingroup\$ Thanks for your input. Maybe 1kV means in fact that you can use it with 250V or 110V without problem... \$\endgroup\$ – JulienFr Sep 1 '15 at 13:31
  • \$\begingroup\$ If you stagger the pins (which is often done in such situations) the pad spacing problem is relaxed. If you use a good quality conformal coating on the board the air creep distance is removed and you just have to trust the dielectric strength of the coating. \$\endgroup\$ – KalleMP Sep 1 '15 at 18:39
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    \$\begingroup\$ The package is fine. The assumption that you are simply going to solder this to a regular board like a regular component is just plain wrong. I think this answer is missing the key points of medium and high voltage design. \$\endgroup\$ – J... Sep 2 '15 at 9:56
  • \$\begingroup\$ @J...: No matter how you mount this part, there will be about 1 kV/mm E field between the C and E pins where they stick out of the package. Also, this is a SOT-89 package, so how else do you propose to mount it other than soldering it to a PC board? \$\endgroup\$ – Olin Lathrop Sep 2 '15 at 10:42
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    \$\begingroup\$ J*... , do you have a product or reference in mind ? How is this coating applied ? \$\endgroup\$ – JulienFr Dec 19 '15 at 18:26
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Yes, you would typically apply a compound to seal the pins after mounting. Even for much larger spacing this is typically done since the leads often have sharp corners (more prone to corona and breakdown). We routinely add something like Corona Dope to even rather large components (HV relays, etc) when the voltage gets up and over 1kV. This provides protection on the order of ~145kV/mm and suppresses both arcs and corona discharge. Surely Corona Dope is not the most suitable compound for this part, of course - it's just to provide the example. In any case, some sort of conformal insulating coating would be required in a system that operated the device to its maximum 1.4kV rating.

What would be of greater concern would be the PCB itself and the traces/pads - the chip is too tight for standard low-voltage PCB materials and design standards (ie: a board made with IPC specified materials). For example, IPC2221A specifications indicate minimum spacing for permanently coated external conductors (ie: chip leads - assuming coated as above) as :

  • 0.8mm @ 500V + 0.00305mm/V additionally
  • --> for 1.4kV this is 0.8 + 900*0.00305 = 3.545mm

Even the internal board traces would have to be spaced further apart (2.5mm, by a similar calculation) than the chip allows. Other considerations for medium or high voltage PCBs is the shape of the pads and traces - these must often be rounded, eliminating sharp corners where traces change direction and using rounded rectangle pads instead of sharp-cornered squares.

So, in addition to needing to coat the component leads with an insulating compound after mounting, a standard PCB designed for low voltage circuits would not be appropriate for this component at its maximum rating. You would therefore need to mount it on a board that was specifically designed for medium voltage (generally ~600-3000V) applications.

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    \$\begingroup\$ The Infineon appnote I linked in my answer mentions that for SMD devices up to 10kV simple silicone tropicalization is reasonable (and probably much cheaper) than what you suggest. \$\endgroup\$ – Fizz Sep 1 '15 at 20:19
  • \$\begingroup\$ @RespawnedFluff Sounds great, you're probably right. I tried to make it clear that I wasn't suggesting, mind you - just using as example. \$\endgroup\$ – J... Sep 1 '15 at 22:43
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It is not clear what the actual minimum distance between the collector and the other pins is but it seems to be a little bit more than 1 mm. Probably in a sealed housing with dry air that would just be sufficient (assuming anyone would use it near the maximum rating !). Another possibility is to apply a conformal coating.

BUT, the fact that the transistor can handle this voltage does not mean you HAVE to operate it up to that voltage. If you operate it at for example 600 V then you would have a considerable margin before the transistor breaks down. In some situations that could be nice to have.

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    \$\begingroup\$ Actually it is quite clear what the minimum distance between the collector and emitter pins is. \$\endgroup\$ – Olin Lathrop Sep 1 '15 at 14:47
  • \$\begingroup\$ Indeed it could be calculated but I was too lazy for that ;-) \$\endgroup\$ – Bimpelrekkie Sep 1 '15 at 14:50
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High voltage primary considerations are clearance and creepage at the physical layer. Clearance is the shortest path between the points of interest and the standard usually used is IPC-2221A. Creepage is the shortest electrical path on the PCB If either of these distances is less than found in the above reference then as you surmise, a compound with better insulating properties is required. The above reference gives values for conformally coated and uncoated boards for surface layers. There are a number of solutions to this issue. This is a simple answer to your specific question. High voltage has many more issues to be taken into account.

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    \$\begingroup\$ Considering that the mentioned standard is fairly costly, I believe it would be very helpful if you would quote from it the actual recommended minimum spacings as they apply to this transistor. \$\endgroup\$ – Oleksandr R. Sep 1 '15 at 14:20
  • \$\begingroup\$ I would be more concerned with clearance than creepage in this case, and they don't even give you enough spacing to put in isolation slots, overall poor choice of package for the part in question. \$\endgroup\$ – Matt Young Sep 1 '15 at 16:59
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    \$\begingroup\$ @MattYoung It's small for a reason - there are plenty of applications where you need to switch low current HV in a very compact assembly. Anyone selecting this component is very consciously trading off ease of integration for the benefit of an exceptionally small package. \$\endgroup\$ – J... Sep 1 '15 at 17:35
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    \$\begingroup\$ @J... By that logic, SOT23 would be better. \$\endgroup\$ – Matt Young Sep 1 '15 at 17:40
  • \$\begingroup\$ @MattYoung You could possibly sell it if you could make it. The size is likely limited by the insulation requirements of the device inside the package. I'd expect this was as small as they could make the die and have it still perform. If not, it may be that the integration expense at SOT23 sizes would be high enough to dry up the market. Every compromise has a sweet spot. This seems to be it, at least for enough people to put the thing up for sale. \$\endgroup\$ – J... Sep 1 '15 at 17:50

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