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I have a question regarding the DDR SSTL termination.

The JEDEC Standard (JESD8-9B) about the SSTL Interface for DDRs shows two possible termination methods, class I with single parallel termination and class II with double parallel termination, Figures 4 and 5 of the Standard respectively.

The thing is that the standard doesn't differentiate between uni- and bidirectional signals (such as data DQ).

Does anyone know if the termination is the same for both signal groups, unidirectional and bidirectional?

Theoretically the Rs series resistor is placed closer to the driver. But with bidirectional signals both sides could act as drivers. Does this mean we have to put two Rs series resistors, one at each side? As far as I know the DDR chips are not internally terminated.

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Original DDR or ddr1 does not have on die termination but later faster versions do.

For plain DDR the recommendation for series termination was either close to the transmitter (controller) or at the middle of the lead in or the trace that came from the transmitter before it splits off to multiple parts. This is the same for address and data.

Similarly vtt end termination is recommended at the end if the line after the DDR parts for both address and data despite the fact That data is bi-directional. For a single point to point DDR it was even recommended to start without vtt termination and then only add if simulation or test demanded it.

Remember DDR was much slower than today's ddr3/ddr4 speeds.

Here's link to a micron app note about it. If you're really interested in learning about DDR I'd encourage you to check out their app notes. They long been a source of good information.

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