I have a question regarding the DDR SSTL termination.
The JEDEC Standard (JESD8-9B) about the SSTL Interface for DDRs shows two possible termination methods, class I with single parallel termination and class II with double parallel termination, Figures 4 and 5 of the Standard respectively.
The thing is that the standard doesn't differentiate between uni- and bidirectional signals (such as data DQ).
Does anyone know if the termination is the same for both signal groups, unidirectional and bidirectional?
Theoretically the Rs series resistor is placed closer to the driver. But with bidirectional signals both sides could act as drivers. Does this mean we have to put two Rs series resistors, one at each side? As far as I know the DDR chips are not internally terminated.