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"minimum tCO = <shortest clock to source register delay> + <micro clock to output delay> + <shortest register to pin delay>" is what I found on this site ( quartushelp.altera.com/15.0/mergedProjects/reference/glossary/def_min_tco.htm )

But if I have the shift register below, with setup time = 2ns and the hold time = 1ns and time for propagation between wires = 0 ns. Can I also calculate the minimum clock to output delay by adding the setup time and hold time and propagation time = 2+1+0=3ns for each flip flop?

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You mention Altera so I assume this is an FPGA design.

If this really is the ideal case (you're ignoring the wire delays due to physical location of the elements) then yes, ideal tCOmin is 3ns. This is the best case (shortest delay, fastest clock) under ideal conditions.

However, post-synthesis simulation will reveal a more meaningful result once the circuit elements have been mapped to specific flip-flops at specific locations on the FPGA. This constrains the available wiring routes, which is where the wiring propagation delay is determined. For a large FPGA chip with high utilization, it becomes more likey that placement is not ideal. Since the worst (longest) tCOmin total delay is what constrains how fast the system can be clocked, the synthesis tools analyze the whole FPGA system and report on whichever circuit has the worst tCOmin, so that the designer can focus their efforts to make a large system perform as required.

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