"minimum tCO = <shortest clock to source register delay> + <micro clock to output delay> + <shortest register to pin delay
>" is what I found on this site ( quartushelp.altera.com/15.0/mergedProjects/reference/glossary/def_min_tco.htm )
But if I have the shift register below, with setup time = 2ns and the hold time = 1ns and time for propagation between wires = 0 ns. Can I also calculate the minimum clock to output delay by adding the setup time and hold time and propagation time = 2+1+0=3ns for each flip flop?