I'm having Synthesis errors on using a VHDL module in Verilog. The error message below says that the type of rd_ptr input in the VHDL module does not match the rd_ptr_integer variable in the verilog code.The compiler also gives this error for the pckt_size output variable. Please help me on this.

The vhdl module entity is this

   entity packet_size is
      fifo_MaxDepth:integer range 0 to 256:=16
    fifo_tlast:in std_logic_vector(fifo_MaxDepth -1 downto 0);
    depth:in std_logic_vector(fifo_MaxDepth -1 downto 0);
    rd_ptr:in integer range 0 to fifo_MaxDepth - 1;
    pckt_size:out integer 
     end packet_size;

The part of my verilog code that is the source of the error is this

 reg [WIDTH-1:0] queue [MAX_DEPTH - 1 : 0];
 reg [MAX_DEPTH_BITS - 1 : 0] rd_ptr;
 reg [MAX_DEPTH_BITS - 1 : 0] wr_ptr;
 reg [MAX_DEPTH_BITS : 0] depth;
 wire [MAX_DEPTH : 0]fifo_tlast_packet;
 wire [MAX_DEPTH_BITS - 1 : 0] rd_ptr_temp;
 integer packet_size_out;
 integer rd_ptr_integer;
 assign num_of_packets=depth;
 assign rd_ptr_temp=rd_ptr;
   // Sample the data
   //initialising the fifo_tlast_packet array for the packet_size module
   genvar    i;
   for (i=0;i<MAX_DEPTH;i=i+1) begin
    assign fifo_tlast_packet[i]=queue[i][0];
    //converting array to integer
    always @(rd_ptr_temp)
      //adding the packet_size module for measuring the packet size of the first fifo data
     #(.fifo_MaxDepth(MAX_DEPTH) )

The errors shown in ISE Synthesis are here

  ERROR:HDLCompiler:440 - "K:/final project/codes/v3/small_fifo_v3.v" Line 69: Formal port rd_ptr of type integer does not match with actual type integer
  ERROR:HDLCompiler:440 - "K:/final project/codes/v3/small_fifo_v3.v" Line 70: Formal port pckt_size of type integer does not match with actual type integer
  ERROR:HDLCompiler:1654 - "K:/final project/codes/v3/small_fifo_v3.v" Line 64: Instantiating <packet1> from unknown module <packet_size>

1 Answer 1


If integer does not match integer this looks like a tool issue with ISE rather than a problem with your design.

First I would eliminate the latter by verifying it in simulation : either ISIM (with some restrictions) or Modelsim should handle mixed designs.

Having confirmed the design, you need a workaround for the tools issue.

If you change the chosen FPGA to something like Spartan-3, ISE defaults to an older VHDL parser which handles some VHDL constructs better, with an "advanced" option touse the new parser instead. Try both... Of course if you need a newer FPGA this won't solve your problem but it may point closer to the problem ... see below.

Alternatively, Xilinx now offers a third VHDL parser in the form of Vivado - maybe this will solve the problem.

(If the problem actually lies on the Verilog side I'm afraid I can't help, if it was my job I'd re-write that little Verilog module in VHDL and be done with it).

If none of the above helps, then you will have to go against my usual advice and actually use std_logic_vector for the port, and whatever the Verilog equivalent is, and the appropriate type conversions to/from integer via (signed or unsigned) on either side.

  • \$\begingroup\$ I had to implement my design on a kintex 7 so I gone with your last advise and the error was solved. \$\endgroup\$
    – MRNakh
    Commented Sep 9, 2015 at 8:32

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