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I've a FPGA design ( I didn't write a single line of sources code) and I've to add a module ( in the design there is a Wishbone bus where it's possible to link others wishbone interface ). The modules linked to the bus are UART and "custom UARTS", there are 16 devices linked to the bus.

In my opinion the design is written really bad ( a lot of long combinational path linked to the wishbone, memory element not registred and a writing code style really caothic and far away to the hardware implementation ) but "it works and close the timing" without my module ( the clk constraints is 125 MHz and the PAR get 125.109 MHz with an occupation of resources of about 50% more or less ).

When I add my module the timing aren't met in several paths. The slow paths are outside my module. Now the question, can I be sure that the problems isn't my module ? Is the PAR report a sufficient way to prove that the problem is the others part of the design ?

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  • \$\begingroup\$ Who makes the synth tools? There are a ton of features there to help analyze this, but I only really know the Xilinx tools. \$\endgroup\$ – Marcus10110 Sep 22 '15 at 0:41
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Since you mentioned "par" it sounds like you're using Xilinx. You should run the static timing report "trce." Run "trce" with verbose timing: "-v 10." This will show the 10 worst paths even if the constraint is met. Sometimes you want to optimize/pipeline/register paths that aren't the very worst ones, because fixing these can help reduce routing congestion, and it lets you meet overall timing closure easier (faster MAP/PAR runs).

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For cases like this, if you cannot or don't know how to change the RTL, you may need a try different synthesis/place and route settings of the FPGA tools. If you are on ISE/Quartus, trying some cost tables/placement seeds may help. On Vivado, it is a different methodology again.

I am not sure what FPGA tools you are using, but there are some tools (InTime), that does this type of exploration more effectively.

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