I've a FPGA design ( I didn't write a single line of sources code) and I've to add a module ( in the design there is a Wishbone bus where it's possible to link others wishbone interface ). The modules linked to the bus are UART and "custom UARTS", there are 16 devices linked to the bus.
In my opinion the design is written really bad ( a lot of long combinational path linked to the wishbone, memory element not registred and a writing code style really caothic and far away to the hardware implementation ) but "it works and close the timing" without my module ( the clk constraints is 125 MHz and the PAR get 125.109 MHz with an occupation of resources of about 50% more or less ).
When I add my module the timing aren't met in several paths. The slow paths are outside my module. Now the question, can I be sure that the problems isn't my module ? Is the PAR report a sufficient way to prove that the problem is the others part of the design ?