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I've been trying to follow: http://www.anandtech.com/show/3851/everything-you-always-wanted-to-know-about-sdram-memory-but-were-afraid-to-ask/3

On this page, they say: "Following activation, the open bank contains within the array of Sense Amps a complete page of memory only 8KB in length."

How can a page of a particular bank be 8KB in length? There are 1024 bits (column lines) on a single row of a bank. Then how does this add up to 8192 bits?

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    \$\begingroup\$ Some DRAM chips are 1 bit wide, others have 4bits, 8bits or 16bits. Page size is multiplicated. In a 64bits wide DDR3 memory stick, there is usually 8 8bits chips (+1 for parity, if any) \$\endgroup\$ – TEMLIB Sep 3 '15 at 19:28
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Every row/column intersection on a DDR3 chip addresses 1 byte wide, not 1-bit. So 1024 columns times 8bytes is 8KB / page (row). From micron's data sheet, I observe that 8 bytes of data are fetched at a time into a FIFO using the upper-address lines of the column address. Then the lower 3 lines of the column address are used to select the particular byte from the FIFO. This is for x8 design. For x16, it would fetch 16 bytes (128 bits) from the row and place it in the FIFO, and then use the lower 3 bits to fetch one of the 8 16-byte data.

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