I'm a software developer learning more about FPGA/VHDL and I wonder if using sequential languages for too long makes it harder to think about hardware.
My question is about connecting components together and I'm sure this is a very basic thing but I can't find a proper answer.
Assume I have an ALU component that has as input two 8 bit data items A(0-7) B(0-7) and an output O(0-7) as well as as operation to perform "OP". It will have a clock input too "CLK". It has the code in a "if rising_edge(clk)" statment
Now my understanding is that the output of the component will be set only on the rising edge of the clock, or importantly a very short time after this due to propagartion delays.
However I have a memory component too.
This has address A0-10, Data inputs D0-7 and a CLK. On the rising edge of the clock it stores the data in the address.
However there is a problem here. At the rising edge of the clock the output from the ALU isn't quite ready yet so what will the memory store? It seems like it would be a bit random as to whether it gets the new or the old output from the ALU depending on how quickly it manages to change. In code terms we have a race condition depending on if the ALU generates the data first or the memory component manages to sample that data first.
My questions are 1) Is this a real problem or am I missing something. 2) If it isn't a problem, how does it work? 3) If it is a problem how do I solve it (general principles are fine).