Turning a frequency locked loop into a phase locked loop

I want to use a GPS module (with a PPS output) to ultimately generate a 5kHz timing signal that is phase-aligned with the PPS positive edge.

PPS-------MSP430-----DAC-------10MHz VCO-------Divider--------5kHz
/\                            |
|(count pulses in             |
|between PPS edges            |
|inside MCU)                  |
-------------------------------


Thus far, I can generate a stable 10MHz signal (10MHz VCO connected to an MSP430 Launchpad for control), and then I divide this 10MHz signal down to 5kHz using several 74LS90 chips.

• This generates a very stable 5kHz timing signal, but the positive edge of the 5kHz signal, in the pulse of the period, is NOT aligned with the positive edge of the PPS.

• How can I adjust the phase, so that the 5kHz and PPS edges are aligned?

----EDIT Thank you for your comments! Our timing error budget is 1 microsecond, so 100nanosec would be great.

I was under the impression that, IF we use a 10MHz oscillator, and control that to 10MHz with the loop, and THEN divide the result down to 5kHz, then "by default" the 5kHz would be very precise (controlling a 10MHz oscillator to within 1Hz, is 100 nanosec of timing accuracy). If I controlled the 5kHz output, and I'm off by 1Hz, then I'm off by 200 microsec (much bigger timing error). Am I correct in my thinking?

• Exactly how much jitter is allowable on your 5 kHz wrt the 1 Hz master? If 100 nsec is OK you don't need a PLL. – WhatRoughBeast Sep 4 '15 at 14:29
• You need to incorporate the output of the divider, in addition to or instead of the input, in the feedback loop to the MCU. – Dave Tweed Sep 4 '15 at 14:46
• If you used the MSP430's own counter/timers instead of the 7490 you could reset their state on detecting the PPS edge. – user_1818839 Sep 4 '15 at 16:58
• You can use directe digital synthesis techniques to generate your 5 kHz square wave. Implement some simple algorithm (for example a PID algorithm) that updates the frequency tuning word of your DDS every time you get a PPS edge. This is basically a digital phase lock loop. Let me know if you want me to expand on any of this. – mkeith Sep 4 '15 at 17:40