I'm trying to design a driver for a 35x7 flip-dot display I picked up from scrap today. The plan is to put a half bridge at each column and row so at each pixel there's a full bridge. For this display, that means 2*(35+7) = 84 transistors are needed. Because I don't want to actually solder 84 things if I can avoid it, I want to use full H-bridge FET chips, c.f. the DMHC3025LSD.

The display requires something like 8V to flip the dot which broadly speaking no microcontroller can do so the PFETs in the bridges can't turn off. To solve that problem I've added an inverting N channel level-shifter (using UM6K1Ns and a pullup) to each PFET which has the bonus of being fail-safe by initializing the PFETs to off when powered on.

Here's an abbreviated schematic:

enter image description here

This leads up to the following: The UM6K1Ns have a very tiny gate capacitance, 13pF, and the DMHC3025LSDs are substantially more, 5.4nC. The microcontroller I want to use, the PIC32MZ2048EFM144 has a maximum supply current of 150mA and a pin limit of 15-33mA (pp. 611 of datasheet). Now, I know that gate charge is the product of the gate current and transition time, but I don't know what would happen in this case since I don't know how the uC supplies current. I suspect that each FET would try and draw the maximum allowable and, because there's 84 of them, overload the microcontroller. What I would hope happens would be the the uC would distribute the 150mA and they would all transition slower.

What can I expect to happen in this case?

If this overloads the microcontroller, what can I do to work around it? Is daisy chaining shift registers my only option?

  • \$\begingroup\$ How many of those 84 outputs will you be switching state simultaneously? If you can limit it in software to (say) 8 at a time then your per-pin current butget can be much larger - e.g. you can use 300R rather than 3K in Nils' answer. Then RC < 2 uS so natural software delays will probably prevent overcurrent (+ a few NOPs if you're cautious) without visibly affecting the display. \$\endgroup\$ – user_1818839 Sep 6 '15 at 11:51

I wouldn't trust that the microcontroller distributes the current for you. If you draw to much current you'll exceed the maximum power rating, and this can blow the chip.

However, how about adding a series resistor between each GPIO pin and each FET gate?

You have a budget of about 1.78mA per pin (150 mA /84 pins). With a supply voltage of 5V that'll give you a resistance of 2.8 kOhm. 3.1k would be the next higher standard value. You want to be on the safe side, right?

For 3.3V it's 1.8k and the next higher standard value would be 2.2k.

That'll limit the short inrush current even if all fets switch at the same time. The drawback is a slight delay because the series resistor and the gate capacitance are a low-pass filter. I would expect this to be neglible for your application because flipping the mechanical dot is likely to be several magnitudes slower than the electrical delay.

  • \$\begingroup\$ How quickly do you need to flip the dots on the display? \$\endgroup\$ – Kevin White Sep 6 '15 at 23:18

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