I'm trying to design a driver for a 35x7 flip-dot display I picked up from scrap today. The plan is to put a half bridge at each column and row so at each pixel there's a full bridge. For this display, that means 2*(35+7) = 84 transistors are needed. Because I don't want to actually solder 84 things if I can avoid it, I want to use full H-bridge FET chips, c.f. the DMHC3025LSD.
The display requires something like 8V to flip the dot which broadly speaking no microcontroller can do so the PFETs in the bridges can't turn off. To solve that problem I've added an inverting N channel level-shifter (using UM6K1Ns and a pullup) to each PFET which has the bonus of being fail-safe by initializing the PFETs to off when powered on.
Here's an abbreviated schematic:
This leads up to the following: The UM6K1Ns have a very tiny gate capacitance, 13pF, and the DMHC3025LSDs are substantially more, 5.4nC. The microcontroller I want to use, the PIC32MZ2048EFM144 has a maximum supply current of 150mA and a pin limit of 15-33mA (pp. 611 of datasheet). Now, I know that gate charge is the product of the gate current and transition time, but I don't know what would happen in this case since I don't know how the uC supplies current. I suspect that each FET would try and draw the maximum allowable and, because there's 84 of them, overload the microcontroller. What I would hope happens would be the the uC would distribute the 150mA and they would all transition slower.
What can I expect to happen in this case?
If this overloads the microcontroller, what can I do to work around it? Is daisy chaining shift registers my only option?