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I'm trying to use a test bench to simulate a 4-input XOR function. I've specified the test inputs and expected outputs in a test vector file. This isn't homework, just for personal interest. For the first 8 (0000 through 0111) inputs, the expected output is being misread from the test vector. The final 8 are okay.

I used the test bench to verify a different combinational circuit, and it worked fine. I modified slightly to simulate my XOR function, and now it is not working as expected.

Any help, comments, suggestions, etc. are appreciated!

XOR module:

module xor_4(input [3:0] a, 
                output y);

assign y = ^a;

endmodule

Testbench:

module testbench3();
reg clk, reset;
reg a, b, c, d, yexpected;
wire y;
reg [31:0] vectornum, errors;
reg [3:0] testvectors [10000:0];

// instantiate device under test
xor_4 dut({a, b, c, d}, y);

// generate clock
always
    begin
        clk = 1; #5; clk = 0; #5;
    end

// at start of test, load vectors
// and pulse reset
initial
    begin
        $readmemb("xor_4.tv", testvectors);
        vectornum = 0; errors = 0;
        reset = 1; #27; reset = 0;
    end

// apply test vectors at rising edge of clock
always @ (posedge clk)
    begin
        #1; {a, b, c, d, yexpected} = 
              testvectors[vectornum];

    end

// check results at falling edge of clock
always @ (negedge clk)
    if (~reset) begin
        if (y !== yexpected) begin
            $display ("Error: inputs = %b", {a, b, c, d});
            $display (" outputs = %b (%b expected)", y, yexpected);
            errors = errors + 1;
        end
        //$display (" %b %b %b %b %b ", a, b, c, d, yexpected);
        vectornum = vectornum + 1;
        if (testvectors[vectornum] === 4'bx) begin
            $display ("%d tests completed with %d errors", vectornum, errors);

            $finish;
        end
    end

endmodule

Test vector:

0000_0
0001_1
0010_1
0011_0
0100_1
0101_0
0110_0
0111_1
1000_1
1001_0
1010_0
1011_1
1100_0
1101_1
1110_1
1111_0

Output from iverilog script:

C:\iverilog>iverilog -o test testbench3.v xor_4.v
C:\iverilog>vvp test
 WARNING: testbench3.v:17: $readmemb: Standard inconsistency, following 1364-200
.
 WARNING: testbench3.v:17: $readmemb(xor_4.tv): Not enough words in the file for
the requested range [0:10000].
Error: inputs = 0000
  outputs = 0 (1 expected)
Error: inputs = 0001
 outputs = 1 (0 expected)
Error: inputs = 0010
 outputs = 1 (0 expected)
Error: inputs = 0011
 outputs = 0 (1 expected)
Error: inputs = 0100
 outputs = 1 (0 expected)
Error: inputs = 0101
 outputs = 0 (1 expected)
Error: inputs = 0110
 outputs = 0 (1 expected)
Error: inputs = 0111
 outputs = 1 (0 expected)
        16 tests completed with          8 errors
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  • 1
    \$\begingroup\$ The first stage is obvious : after reading in the vectors, print them right out. My guess is they will print out wrong, and you're not reading the vector file you think you are. \$\endgroup\$ – Brian Drummond Sep 6 '15 at 13:48
2
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The clue is in the warning messages at the beginning of the simulation:

WARNING: testbench3.v:17: $readmemb: Standard inconsistency, following 1364-200 .
WARNING: testbench3.v:17: $readmemb(xor_4.tv): Not enough words in the file for the requested range [0:10000].

Each entry of testvector is 4 bits wide, however xor_4.tv is 5 bits and {a,b,c,d,yexpected} is also 5 bits.

Change reg [3:0] testvector [10000:0]; to reg [4:0] testvector [0:10000];

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  • \$\begingroup\$ Lovely, that fixed it. Also had to change if (testvectors[vectornum] === 4'bx) to if (testvectors[vectornum] === 5'bx), otherwise it won't display the total number of test errors. \$\endgroup\$ – Danny Sep 6 '15 at 17:50

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