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I'm trying to make a "Toggle Latch" or toggle flip flop. The S-R latch works properly (The two NOR gates). when I add the two AND gates, the output led turns off and it does not respond to the inputs J and K !

I tried to add pull-up or pull-down resistors but it does not work too.

The IC's I'm using are 7408 and 4001 and I'm sure they are working.enter image description here

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I can think of several possible reasons why you're having problems.

The first is that you are trying to connect 7400 and CD4000 series directly, and that is not a good idea. At the least, put a 1k pullup on the outputs of the 7408s. If you check the data sheet, you'll see that Voh (high output voltage) is only guaranteed to reach 2.4 volts, which is not enough (3.5) to reliably drive 4000-series gates. Even better, replace your 7408s with CMOS gates such as 74HC08.

The second possibility is the fact that you haven't shown your LED connections (and worse, you apparently are driving your LED directly from your logic - 4000 gates have very low current capabilities, especially when sourcing current. Try this instead:

schematic

simulate this circuit – Schematic created using CircuitLab

This also addresses the third possibility - you are letting your 7408 inputs float, and think that this will be seen as a low input. It's not. 7400 ICs will generally see floating inputs as a logic HIGH, although they are susceptible to noise when you do this.

The fourth possibility (a low probability, but not zero) is that you have left your two unused NOR gates with their inputs floating. This is a major no-no with CMOS. ALL inputs to a chip must be tied high or low or to a gate output. Unused gates too - I've had unused floating gates corrupt the used gates on a chip, so don't think you can skip this.

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The toggle flip flop circuit you show is a very bad one. For toggling, it works only when the toggle condition is very short, when it is longer it will oscillate. A real JK flip-flop has two memory stages and triggers on the edge of the clock signal, not on the level of an enable signal.

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