We know that to convert unsigned to signed (precisely, I want to convert a pure binary into CA2 number) we must negate the unsigned number adding, then, + 1. In VHDL I can implement an inverter and an adder that manages the carry in. I have two numbers of 32 bits. Is there another way to implement the sum + 1 using anything cheaper? Is there a solution to manage the carry in using only logic gates?
It really isn't worth worrying too much about this detail. Adding 1 to a number is such a common idiom in HDL that synthesis tools have highly-evolved methods for dealing wtih it. Also, most modern FPGAs have dedicated, hard-wired fast carry logic that does not consume logic cells, and that synthesis tools know how to take advantage of.
If it's unsigned, it is by definition positive, therefore it's 2's complement equivalent is also positive, therefore the bit pattern representation is the same.
The one difficulty arises if its MSB is already set : then it is an unsigned too large to represent as a signed number of the same size. So the completely general answer is to sign-extend it into a 2's complement number at least 1 bit wider :
my_signed <= '0' & my_unsigned;