For design of a synchronous buck converter (which would be used to charge the battery) which would be driven by Micro-controller's PWM output, i selected the IRLB8748 NMOS Power transistors (for both high and low side switches) which would be driven by the gate IC NCP5351. As its my first time, while going through the data sheet of the driver IC NCP5351 (page 7, Figure 3) I found the concept of the BOOST capacitor. Searching more for it I found the purpose of its use and also the method to calculate its value.

So for the capacitor's value calculation purpose I followed this design document from Silabs and calculated the value of capacitor and the resistor which would be needed in my case.

But i have a few confusions, which i needed to clear:

(My application specifications are : Vin = 12V , Vout = 4.5 , DutyCycle(max) = 0.375 , Switching Freq = 62.5kHz).

1) In the Design document (at Page 4, 2.2 Design Example) the value of Ib (supply bias current) is needed for the calculation of Eq. 1. I found this value for my case to be 50uA, given in NCP5351's datasheet page 5 (given as VBST Quiescent Current, Operating). So is this the right value to be chosen for my case for Equation 1's calculation ?

2) For equation 2, the value of Maximum allowable Ripple was taken to be 5% of VDD. What significance does this value has ? I also did the calculations in my case using 5% for this value. I hope it works fine.

3) If we look at the NCP5351 's Data sheet (page 7, Figure 3), the connection of the resistor and the boot capacitor is not the same as it is in the Design document in Figure 1 and Figure 2. The resistor in the design document is placed in series with the Diode and the Capacitor, however in the NCP5351's datasheet page 7, the connection is a bit different. So can i calculate the values for my Resistor and the Bootstrap capacitor (which turned out to be 21.5 Ohms and 93.2nF respectively), and place them like they are in NCP5351's datasheet page 7 ?

4) In NCP5351's datasheet page 3, its written that In conjunction with a Schottky diode to VS, a 0.1 uF to 1.0 uF ceramic capacitor connected between BST and DRN develops supply voltage for the high−side driver (TG).. However the value for the Resistor is not given. Does that mean that i will select the value of the resistor which i calculated by the above mentioned Design Document ? (As the value of the capacitor that i caluculated came out to be 93.2nF which is approx equal to 0.1uF).

5) Also the main question, does This design document that i followed, provides the right way to calculate the Bootstrap Capacitor and Resistor values which would be needed in my case ?

Your helpful comments and suggestions would be appreciated.


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    \$\begingroup\$ Rb largely limits surge current into bootstrap cap or drive terminal. Usually can be low or zero - but do decide if IC can handle the current spike. Bootstrap pin Iq is probably NOT the main lpoad. The object is to provide energy to charge the FET gate capacitor. Power needed is (0.5 x Cgate x Vgs^2) x freq. ie the energy stored in the gate capacitance is half C V^2 and this is added once per cycle and then remioved when the FET is turned off and then added again next cycle. If Cb ~= Cgate then the voltage on Cb will be halved when charged Cb is connected to discharged Cgate..... \$\endgroup\$ – Russell McMahon Sep 8 '15 at 12:25
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    \$\begingroup\$ .... If Cb is say 10 x Cb then voltage on Cb will drop by ABOUT 10% when Cb is used to charge Cgate. If Cb is too small the voltage on Cb will drop greatly during gate charging and MAY fall too low to be effective depending on FET Vgsth etc. If Cb is very large compared to Cgate you may waste power and have to manage the inrush current when charging more effectively. .... \$\endgroup\$ – Russell McMahon Sep 8 '15 at 12:26
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    \$\begingroup\$ .... You could use the gate charge in nano Coulombs to work out power needed (and this is a usual approach) but as a good quick guide - your FET gate capacitance is about 2 nF and you suggest using 93 nF as Cb so the voltage on Cb will fall very little when yuou connect Cgate SO that seems large enough. Probably 47 nF or maybe 22 nF would be OK "off the cuff". \$\endgroup\$ – Russell McMahon Sep 8 '15 at 12:26
  • \$\begingroup\$ Since no one else answered, ill assume 22nF or 47nF to be the suitable value, and try with it. However i'm confused that if our Cb ~= Cgate like you explained, then why did i get a value for Cb, which is approx 50 times the Cgate value, using this design document. Secondly im still not sure about the value of R, or even whether to place it or not. And thirdly, I don't know IF ill be placing a R in my circuit, would i be doing it in the way by which NCP5351's datasheet did or not, as it seems quite different from the one in the Si design document (which is series conn. of R,C and diode). \$\endgroup\$ – yiipmann Sep 10 '15 at 14:45
  • \$\begingroup\$ I didn't mean to suggest that Cb ~= Cgate - Ratjer that if it is say about 10x larger you will get ABOUT 10% ripple (1/10) when the gate cap is charged and if it is 50x larger you get about 2% ripple (1/50) AND 2% may be far smaller than is necessary if the cap charge to well above Vgsth. SO the app note value of say 98 nF is about 50 x Cgate and the designers may feel that is OK. My comments re resistor gives a guide Time constant max should be such that cap will recharge in one switching period (and if it does not discharge much the TC may be far longer than a cycle AND R should prevent .... \$\endgroup\$ – Russell McMahon Sep 11 '15 at 15:48

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