VHDL functions with generic or "run time variable", synthesis issues

Question

I have been thinking about functions in VHDL. If we have a function we could have both a function where we pass a "generic" (i.e. a fixed parameter known at compilation time) and a variable/signal (which contents is know at "execution" time).

So what I was considering were.. if in a function we pass as input a "generic parameter" and only such parameter it means that basically such function is an expression which result is deterministic, otherwise because the input could vary anytime.

How such situation affect a synthesis? Would the compiler synthesize a register with the expression evaluation result? or would it try to synthesize some extra logic too?

As instance suppose we have an entity (there will be some syntax error on purpose)

entity ent
 generic(n : unsigned);
 port(x : in unsigned; ...);
end entity;

architecture arch of ent is
  function my_f(i : unsigned) return unsigned is
    variable k : unsigned;
  begin
    -- something
    return k;
  end function;
begin
  --body
  -- end body
end architecture arch;

What is the difference (in terms of synthesis if there is) if do a call like

y <= my_f(n); -- i'm using a generic

instead of

y <= my_f(x); -- i'm using the input

The parameter n wouldn't change at run time, instead x (as stimulus) could change anytime. So would the synthesis tool synthesize all the necessary logic to manipulate n in the first case? or would it be smart and simply it would evaluate the function and will substitute the result in a possible assignment?

Hoping it's better now.

Answer 1

Synthesis tools work very hard to evaluate everything at compile time that they possibly can. For everything else, they synthesize logic -- including function calls, assuming that the function is synthesizable (some are not).

Therefore, the answer to your question is, "it depends". It doesn't matter if the actual parameter to the function is a generic or a signal (port) -- if the value is known at compile time, the synthesis tool will evaluate the function at compile time and use the result. The only difference is that a generic is by definition known at compile time, while a signal may or may not be.

If the function needs to be evaluated at run time, then the synthesis tool will generate the logic required to do that, assuming that no non-synthesizable constructs have been used in the body of the function.