# VHDL functions with generic or “run time variable”, synthesis issues

I have been thinking about functions in VHDL. If we have a function we could have both a function where we pass a "generic" (i.e. a fixed parameter known at compilation time) and a variable/signal (which contents is know at "execution" time).

So what i was considering were.. if in a function we pass as input a "generic parameter" and only such parameter it means that basically such function is an expression which result is deterministic, otherwise because the input could vary anytime.

How such situation affect a synthesis? Would the compiler synthesize a register with the expression evaluation result? or would it try to synthesize some extra logic too?

As instance suppose we have an entity (there will be some syntax error on purpose)

entity ent
generic(n : unsigned);
port(x : in unsigned; ...);
end entity;

architecture arch of ent is
function my_f(i : unsigned) return unsigned is
variable k : unsigned;
begin
-- something
return k;
end function;
begin
--body
-- end body
end architecture arch;


What is the difference (in terms of synthesis if there is) if do a call like

y <= my_f(n); -- i'm using a generic


y <= my_f(x); -- i'm using the input


The parameter n wouldn't change at run time, instead x (as stimulus) could change anytime. So would the synthesis tool synthesize all the necessary logic to manipulate n in the first case? or would it be smart and simply it would evaluate the function and will substitute the result in a possible assignement?

Hoping it's better now.

• It will evaluate the function during synthesis and substitute the result. I have used such functions in a loop in another function to fill a lookup table with data : the result is simply a ROM full of those values. – Brian Drummond Sep 10 '15 at 14:47
• Souns like it is what i was expecting... thank you! – user8469759 Sep 10 '15 at 14:58