# Why are low-dropout (LDO) voltage regulators unstable?

LDO regulators based on P-type transistors seem to be the preferred form of linear voltage regulator today, but I keep hearing about how I have to choose the output capacitor(s) carefully to guarantee stability. The older high-dropout regulators with N-type transistors didn't seem to have this problem. What is it that causes LDOs to be less stable? Is it the P-type transistor? The smaller difference between $V_{in}$ and $V_{out}$? Both? Or something else altogether? And why is the ESR of the output capacitor so important?

A LDO is a control loop. And like all control loops, there is always room for instability.

So how do you make a control loop stable ?

1. You provide sufficient phase margin (difference in phase from when the gain crosses the 0 dB axis and 180.
2. The slope of open loop plot should be -20db/dec when crossing the 0dB axis
3. Provide sufficient gain margin

If you we look at a typical open loop response of an LDO, it may look like this

There are a number of poles.

1. Error amp pole - a pole due to the amplifier
3. Parasitic pole - usually within the pass element (not shown in this image).

There is also one zero in this image.

1. ESR Zero - a zero due to the output capacitor

If you look at point 2 of a stable loop, it says that the slope should be -20db/dec.

Well, what if...the zero was never there. That means that the slope when it hits 0db, is -40db (due to the two previous poles). Instability.

Adding a zero before the 0db axis, makes the system stable.

The easiest way to add a zero to the system is through the ESR of the capacitor. You need a capacitor anyways, so you are killing two birds with one stone here.

The ESR matters, because it controls the placement of the zero. It should be low enough so that you can get the -20db/dec when you cross the 0db axis but low enough that the gain is below 0 dB before the next pole (usually due to the parastics).

• I find it odd that the slope of the bode actually has a direct effect on stability. Doesn't that really mean that a -20dB slope will guarantee a phase of -90°, which means infinite gain margin, whereas a -40dB slope will make the phase drop to -180°, giving a limited gain margin that can be quite low? – Mister Mystère Sep 14 '15 at 11:16
• Both this and LvW's answer are great and answer different parts of my question. Unfortunately, I can only accept one, so I'm choosing the one that got more votes. – Adam Haun Sep 15 '15 at 1:59

"The older high-dropout regulators with N-type transistors didn't seem to have this problem. "

The answer is as follows: The npn-type transistor used as a control element is operated in a common-collector configuration (collector potential must be higher than that of the emitter). In contrast - as shown in the figure (provided by efox29) - the pnp type has a collector resistance (the voltage divider) and works as an inverting common-emitter amplifier with gain. Therefore, the non-inv. opamp input is connected to the divider chain (for a total negative loop gain).

That means: The npn transistor with an emitter resistor works as an emitter follower with a non-inverting gain less than unity (and the inverting opamp input terminal must be used). Regarding stability it is important to realize that, therefore, the total loop gain is much smaller if compared with the pnp case. As a consequence, stability problems are reduced (or even disappear). However, as a disadvantage, the smaller loop gain reduces the regulating properties of the whole LDO.

• I thought the LDOs were based on p-channel FETs, not PNP BJTs(?). – Peter Mortensen Sep 12 '15 at 18:45
• It can be either - The LM2940 for example is a PNP BJT version. – Kevin White Sep 12 '15 at 22:27