# VHDL type mismatch error

This is my first question.

I have a package that contains the following type:

type t_rgb_64x48 is array(0 to 47) of std_logic_vector(63 downto 0);


and is being used in my file.vhd file.

file.vhd contains an entity that contains the type of the package mentioned earlier:

RData_in : in t_rgb_64x48;
ColumnAddress_Start : in integer;
ColumnAddress_End : in integer;
RowAddress_Start : in integer;
RowAddress_End : in integer;


It also contains a signal with its corresponding type:

type t_vgaram is array(0 to 479) of std_logic_vector(639 downto 0);
signal s_rstorage : t_vgaram;


I need to access s_rstorage through the following statement:

s_rstorage(ColumnAddress_End downto ColumnAddress_Start)
(RowAddress_End downto RowAddress_Start)
<= RData_in(ColumnAddress_End downto
ColumnAddress_Start)
(RowAddress_End downto RowAddress_Start);


to store the value of RData_in to s_rstorage and making sure that they are of the same width in 2D.

The problem is this error:

Type of s_rstorage is incompatible with type of RData_in.

I know that they have different types as the cause of the error. But how do I fix this problem?

## 1 Answer

Arrays of arrays are a bit of a pain. Can you use a 2-d array? You'll still need some slicing functions but it might be more pleasant.

Are you hoping to synthesise this? It looks like it'll be very large, if you want to be able to overwrite arbitrary areas of your image in a single clock tick, which seems to be the case with the code you describe.

• Looks like what I call The Multiplexer-Flip-Flop Monster. It tend to come you if you think your inferring RAM blocks and are not careful enough with your coding style. – trondd Dec 11 '12 at 19:57