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I am designing a circuit that switches between 2 power supplies, controlled by a MCU. The circuit is the following.

enter image description here

This is for a simple supply line, so it will be duplicated for both PS.

As you can see, when the switch (uC) is tied to ground, NPN is open, and I have 23.9V in the gate of MOSFET, which closes the device (VGS > 2.4, http://www.onsemi.com/pub_link/Collateral/MGSF1N03LT1-D.PDF) allowing the current flow from the drain to the source and to the LOAD resistance, which represents the MCU and another circuits.

The U4 ammeter shows a 1.04A current, that flows through the MOSFET, so if I am right, the voltage dropped on the transistor is about 1.04xRds, and the Rds for this transistor is about 100 mohms. But the U3 voltmeter shows that 3.1V are dropped along the transistor, which appears to be a huge value.

Am I ignoring any point about the design? Is it about the simulator?

Thank you in advance.

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  • \$\begingroup\$ Its a common trap, you build a source follower ! Let me find an answer for you... Hmm, cannot find one, will write an answer for you \$\endgroup\$ – Bimpelrekkie Sep 15 '15 at 7:50
  • \$\begingroup\$ 20V is the abs max rating for the gate-source voltage. Read the data sheet. Also, what are those U things? \$\endgroup\$ – Andy aka Sep 15 '15 at 8:31
  • \$\begingroup\$ They are voltage meters \$\endgroup\$ – Bimpelrekkie Sep 15 '15 at 8:57
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What you build is a source follower which acts sort of like a voltage copier, it copies the gate voltage to the source (with a Vgs drop in voltage).

What is needed for Rds to be as low as you want it is that Vgs is maximised so the source needs to be grounded.

Alternatively you can use a PMOS if the grounds need to be common. Do note that the polarity at the gate of the PMOS switch is reversed compared to an NMOS ! Note also that the PMOS circuit is the same as the middle NMOS circuit but upside-down !

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ Great, I was suspecting that my VGS was so close to the threshold... If I use the third option (PMOS), switching the transistor with 24 VDC, I have to choose a device that supports a Vsg near to -24 V, which is a bit strange (most of transistors I've seen supports up to -20V). In this case, is there any problem if I place a zener on the NPN's collector to increase VSG? Thank you so much! \$\endgroup\$ – jmigue Sep 15 '15 at 8:42
  • \$\begingroup\$ There is no need to use a zener to prevent Vgs becoming too large, just split R1 in your schematic in 2 x 5 kohms in series and then connect the gate of the PMOS in the middle of the two resistors, then Vgs will be halved. See schematic no 4. \$\endgroup\$ – Bimpelrekkie Sep 15 '15 at 8:52

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