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Follow are two figures. The first one is basic AZ circuit and autozeroed signal, which is a simple RC circuit with a switch. The second figure is about the voltage shows in the first one.

enter image description here enter image description here

Operation Principle: phase 1 is to control the switch on/off. Each time switch S is closed, the output voltage Vaz is reset to zero and the noise source voltage Vn appears across resistor R and capacitor C. Assuming RC << Taz, at the end of sampling phase ( when switch S opens ) the noise voltage Vn is sampled onto capacitor C. The output voltage becomes equal to the difference between the instantaneous voltage Vn and the voltage Vc stored on capacitor C.

Question : I do not understand when the input Vn is varying like sinusoidal signal with a DC average, the Vc node is varying like the shown in Figure. 1) When switch is on, the Vc is suddenly according with the level of Vn, I mean, why it is like this ? why the capacitor should not charge/discharge after comparing the Vc is lower/higher than the input voltage ? 2) Even for so, during the switch is on, why the capacitor is exactly varying like the input signal ? The resistance why dont get any voltage distribution ?

Above are my questions, I think it maybe simple or I just miss some clear point here. This circuit and description is coming from a paper attached below, and its figure 2 on second page. The description of the circuit is on third page left down. Welcome any suggestions for my confuse. Thanks for the help.

http://www.bioee.ee.columbia.edu/courses/upload/Bibliography/enz_procieee_1996.pdf

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I do not understand when the input Vn is varying like sinusoidal signal with a DC average, the Vc node is varying like the shown in Figure

When the switch is open circuit the voltage previously deposited on the capacitor remains at that level until the switch closes again. An open switch prevents charge leaving the capacitor.

When switch is on, the Vc is suddenly according with the level of Vn, I mean, why it is like this ?

When the switch closes the capacitor rapidly charges (via R) to Vn - it has no option to do anything else.

why the capacitor should not charge/discharge after comparing the Vc is lower/higher than the input voltage ?

I really can't understand this question - please rephrase

The resistance why dont get any voltage distribution ?

There will be finite charge times and small errors in the accumulated voltage on the capacitor when the switch opens but this happens all the time in sample and hold circuits and the error is minimized by trying to reduce the value of R.

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  • \$\begingroup\$ thanks so much for your answer. for the question I rephrase, I mean, when the switch is on, if the capacitor DC level ( stored before) is higher than the input voltage, why the capacitor can not be seen as a voltage supply which is higher then the input supply and the capacitor should discharge, why it has to be same level with the input ? And also, can I understand like this, the "rapidly charge" honestly takes time to be finished, but in the figure it just sharpely changed, right ? \$\endgroup\$
    – alan
    Commented Sep 15, 2015 at 12:20
  • \$\begingroup\$ If the capacitor is charged higher than the input voltage, when the switch closes the cap will discharge to the input voltage level. There will be no instant change and I think you understand this now. The diagram is not perfect! \$\endgroup\$
    – Andy aka
    Commented Sep 15, 2015 at 12:23
  • \$\begingroup\$ I think I understand, I miss the point that the resistance is quite small and the rapid charge could take time too. Thanks a lot for your help, Andy. \$\endgroup\$
    – alan
    Commented Sep 15, 2015 at 12:40
  • \$\begingroup\$ No problems and if you have further questions related to this question please ask else consider marking this answer as "accepted". \$\endgroup\$
    – Andy aka
    Commented Sep 15, 2015 at 12:47

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