I am designing a circuit board that has an SPI bus with 32 slaves. I plan to drive the bus at 8 MHz. Another individual on this site commented on a previous post of mine that the total capacitance from all the slaves might limit the maximum rate.
I went ahead and tried that calculation. The capacitance of the GPIO pin on the MCU is 30 pF and the capacitance on the CLK lines for the slave is <10 pF. I compute the resistance of the CLK trace to be 0.6 ohms using an online trace calculator (8 mil, 1 oz/ft, 20 cm total length)
C = 30 pF + (32*10 pF) = 350 pF R = 0.6 ohm tau = RC = (350 pF)(0.6 ohm) = 0.2 ns t_rise = 2.2 * tau = 0.44 ns
I was able to probe a similar board with 16 slaves (predecessor to the board I'm designing) and found the rise time to be 18 ns. I made sure to set the probe to 10X.
So my question is: where am I going wrong here? Do I need to take into account the output resistance of the GPIO as well?