I've worked on an FPGA dev board, (The DE0), but never designed an application using the chip alone. On the board I have, there's alot of components, and I'm not sure which ones are necessary for designing a standalone circuit.

I know that the EPC4S is important, because it holds the .pof, and I would want a USB controller, but there's about 20 other chips on there. Can anyone explain what the bare minimum an FPGA would require if ignoring the different connectors and peripherals?

  • \$\begingroup\$ The FPGA and the chip that holds the FPGA programming. \$\endgroup\$ Sep 15, 2015 at 20:51
  • 2
    \$\begingroup\$ And many bypass capacitors, more than 100 of them in some cases. \$\endgroup\$ Sep 15, 2015 at 20:58
  • \$\begingroup\$ Don't forget 5 or 6 power supplies... \$\endgroup\$
    – The Photon
    Sep 15, 2015 at 21:40
  • \$\begingroup\$ Also an active crystal oscillator, unless you take clock signal from the USB controller. \$\endgroup\$
    – venny
    Sep 15, 2015 at 21:46
  • \$\begingroup\$ I figured I'd need caps, but how do you choose where they go and how big they need to be? \$\endgroup\$
    – Zephyr
    Sep 16, 2015 at 0:43

1 Answer 1


You don't need much. Here's a list of what you might need:

  1. FPGA itself
  2. FPGA configuration source
    • SPI flash + some method of programming it (direct or indirect via JTAG) (cheapest)
    • JTAG programmable FPGA config flash (more expensive, but quite convenient)
    • Parallel or serial load from external controller
    • For some FPGAs, small config flash + load core over PCIe after enumeration
    • Integrated with FPGA (this is not common, but some FPGAs support this - e.g. spartan 3AN)
  3. Voltage regulators
    • Core supply
      • generally very low voltage, 0.9 to 1.2 volts
      • might need quite a few amps for a large FPGA (maybe around 100 to 500 mA for a small FPGA, can be up to 20 or 30A for a very large FPGA, FPGA size (static power), design size, clock speed, and activity factor dependent)
      • DC-DC converter recommended as LDO will be very inefficient
    • Might need auxiliary supply/supplies for other internal logic, generally 2.5 to 3.3v
    • I/O supply, might need multiple voltages depending on design
    • Might need termination voltages (Vtt) or reference voltages (Vref) for certain high speed interface standards
    • High speed transceivers generally need dedicated linear regulators
      • two stage approach of DC-DC converter followed by LDO with separate bias supply (say for a 1.2V rail, use a 1.3 to 1.5V switcher followed by an LDO with a separate bias supply input from the 2.5v or 3.3v rail)
  4. Bypass caps
    • Gobs and gobs, approximately one per couple of power pins
    • Might need combination of small and large caps for low and high frequency coverage, especially for high speed transceivers
  5. Clock source(s)
    • Need at least 1 oscillator for user logic routed to a global clock pin
      • Use oscillators, not crystals as FPGAs generally cannot drive crystals
      • Pick a relatively reasonable frequency as you can use internal DCMs/PLLs to rescale it (check FPGA clocking documentation)
      • Consider using clock enables instead of generating slow clocks, this will reduce the number of required DCMs/PLLs as well as removing/simplifying clock domain crossing issues
      • Frequencies that need to be very precise could require dedicated oscillators
    • High speed transceivers generally require dedicated oscillators and external clock management (clock buffers, clock muxes, jitter attenuators, PLLs, etc. possibly requiring power-on initialization via I2C)

I just recently put together a small board with a spartan 3 FPGA, Winbond SPI flash, FTDI FT2232 USB interface chip, and shared 12 MHz silicon oscillator. OpenOCD can drive the FPGA JTAG interface via port A of the FT2232 to program the FPGA and then program the SPI flash through the USER1 JTAG instruction after the FPGA configuration is loaded. The 2nd port of the FT2232 can then be used as either a serial port or as a USB FIFO. The USB FIFO interface requires 14 pins, but it can run at 8 Mbyte/sec and it appears as a standard serial port on the computer, making the software interface trivial.

  • \$\begingroup\$ So how would I go about designing such a board? If I can't try a design before making a pcb, how can I tell where I need caps and how big they should be? \$\endgroup\$
    – Zephyr
    Sep 16, 2015 at 0:43
  • \$\begingroup\$ There are lots of guidelines for how to size and place the caps. I would recommend looking at existing dev boards to see how it is done there, and then implement something similar. The bypass caps actually aren't extremely critical, so long as they are low ESR and they are placed relatively close to the pins. Sometimes manufacturers will release board design guidelines that detail this sort of thing. \$\endgroup\$ Sep 16, 2015 at 3:11
  • \$\begingroup\$ As far as bypass capacitors go, the 'standard issue' bypass cap is generally 0.1 uF. And from looking at the DE0 schematic, it seems like they have between 1 cap per every 2 or 3 power pins, which is probably reasonable given the number of power pins on the chip. The Spartan 6 dev board SP605 uses 2.2 uF caps with on the order of 1 cap per 3 power pins along with about 1 10 uF cap per 6 pins or so for bulk capacitance. The MGT banks are bypassed a bit more carefully, with one 0.22 uF cap per pin and two 4.7 uF caps per bank. \$\endgroup\$ Sep 16, 2015 at 3:27

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