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I having troubling understand what other interrupt firing high_isr besides TMR2 on PIC18f4550.

Way I detect it I set pin MY_DBG_PIN toggling everytime high_isr is activated, and from what I try to do, only TMR2 I have activated and nothing else.

My code looking like:

#include <p18f4550.h>

#define USE_OR_MASKS

#include <pwm.h>
#include <timers.h>

#pragma config PLLDIV = 10
#pragma config FOSC = ECPLLIO_EC

#pragma config PWRT = OFF
#pragma config BOR = OFF
#pragma config MCLRE = ON
#pragma config PBADEN = OFF
#pragma config ICPRT = OFF
#pragma config LVP = OFF
#pragma config WDT = OFF,DEBUG=OFF

/* Sets the PWM value on CCP1 to 50% duty cycle*/

#define MY_DBG_PIN        LATBbits.LATB1 
#define MY_DBG_PIN_TRIS   TRISBbits.TRISB1

#pragma interrupt high_isr
void high_isr (void)
{
    //* Comment to notice toggling of MY_DBG_PIN at 0.7Mhz
    if(PIR1bits.TMR2IF)         // Timer 2 interrupt
    {
        MY_DBG_PIN = 0;

        PIR1bits.TMR2IF = 0;
    }
    //*/

    // Are some other interrupts also firing? Why?
    //MY_DBG_PIN = 0; // If uncomment, toggling at 0.7Mhz
}

#pragma code high_vector=0x08
void interrupt_at_high_vector(void)
{
    MY_DBG_PIN = 1;
    _asm GOTO high_isr _endasm
}
#pragma code /* return to the default code section */

void main (void)
{
    TRISC=0;
    OpenTimer2(TIMER_INT_ON | T2_PS_1_4 | T2_POST_1_16 );
    OpenPWM1( 149 );
    SetDCPWM1( 300 );

    MY_DBG_PIN_TRIS = 0;    // make it an output 

    PIE1bits.TMR2IE=1;           //enable Timer2 interrupt
    INTCONbits.PEIE=1;          //enable peripheral interrupts
    INTCONbits.GIE=1;           //enable glogal interrupts
    INTCONbits.GIEH = 1; /* Enable global Interupt */

    while(1)
    {
    }
}

As can see, only TMR2 possibly fire ISR, but then do you notice high freq. update of debugging pin if you uncomment the line?

If I specify TMR2 interrupt flag in ISR and then toggle debugging pin, then expected update freq, as current active code is like.

What other thing can be triggering ISR and how I check that without checking flags of all interrupts?

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  • \$\begingroup\$ Simple coding practice that I follow, every possible ISR has code. In that code that should not be called have a second pin you can raise high. \$\endgroup\$ – Kortuk Sep 5 '11 at 3:55
  • \$\begingroup\$ @Kortuk: I not really understanding what you say. Can you expand please to help me learn? \$\endgroup\$ – sekharan Sep 6 '11 at 2:32
  • \$\begingroup\$ Solved. No other interrupt firing but problem was I did not have line 'PIR1bits.TMR2IF = 0;' for second (currently commented) bit. Thanking Oli Glaser! \$\endgroup\$ – sekharan Sep 6 '11 at 2:33
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    \$\begingroup\$ even though you may not be using other interrupts that exist please take the time to make code to cover the case if they are triggered. In the code for this raise a pin high, or if you are still on debugger, disable WDT and go into an infinite loop. This way you will find out if you are triggering an interrupt you should not be. You do not want an error somewhere to give you a once a month error on a product that is impossible to track down. \$\endgroup\$ – Kortuk Sep 6 '11 at 10:03
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If I understand right, then when you comment the first (larger) bit out and uncomment the second bit it toggles at 0.7MHz?
The interrupt flag is not cleared so it will immediately jump back to the ISR. The second bit is not in an if statement so it will always be executed. So it will keep setting the pin in the interrupt_at_high_vector and clearing it in high_isr. You need to make sure the flag is always cleared (if it is not cleared automatically)
What are you wanting it to do?

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  • \$\begingroup\$ Both your assumptions correct, and you also right when you say problem was I did not have line 'PIR1bits.TMR2IF = 0;' for second (currently commented) bit. However, I confusing - how is 0.7Mhz output possible by bit toggle on a 12MIPS core? \$\endgroup\$ – sekharan Sep 6 '11 at 2:31
  • \$\begingroup\$ @SGosh - It would be 68 clock cycles or 17 instructions 1/(17/12e6)) = 705882 kHz. Also, it doesn't have to run at 12MIPS, that's the maximum using the PLL set up for a 48MHz clock. \$\endgroup\$ – Oli Glaser Sep 6 '11 at 10:42

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