I am currently trying to design a circuit for a low voltage cutoff. Once the voltage dropped below a certain threshold it should stay low. When a USB-cable is attached it should reset and start watching the voltage again when the cable is removed.
V+ could be around 2-4.5V
VCC should be 3-4.5V or 0V
The TC54 is a voltage detector which outputs the input voltage as long as it is above a certain threshold. When its lower the output is active low.
By using two npn-transistors in parallel I tried to get some kind of "OR-Gate" that pulls the base of the pnp-Transistor low, when a voltage is applied either the by voltage-detector or the usb-port. Which in turn keeps the voltage-detector alive.
Could this kind of "feedback-loop" actually work, or do I need to add some kind of hysteresis (for example a capacitance)? Is R15 needed? The data-sheet states an absolute maximum 5V for the Emitter-Base-Voltage.
Is it okay to put the transistors in parallel?
I had some doubts because I read a lot about the negative thermal coefficient and that because of that one of the transistors would run hot and take all the current. Does this apply to this case, where the current is so low, that each of the transistors could easily take it on its own?
It would be nice if someone would understand my schematic and could offer a brief feedback.