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I am trying to do something like this:

    `define PORTS 4
    module mulitplexer
    (
      input logic clock,
      
    generate
     for(genvar  n = 0; n < `PORTS; n++) begin 
        output  a_t       multiplx_a_[n],
        input   a_fc_t    a_multiplx_[n],
        input   b_t       multiplx_b_[n],
        input   logic     ready_[n],
     end
   endgenerate

    input logic reset
    );

But, I get a warning about missing a port in the ANSI port list. I have not been able to find any answer to what I am doing wrong. Any help will be much appreciated.

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  • \$\begingroup\$ I don't think you can use for/generate in module definitions. Instead you should use an array and a parameter that defines the size. \$\endgroup\$
    – svens
    Commented Sep 16, 2015 at 13:47

2 Answers 2

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This is something that cannot be done in SystemVerilog; actually several things.

You can't use a generate construct in the middle of a another construct, in your case, a module header declaring a port list. And even if you could, you cannot use generate to build an identifiers like logic ready_0, ready_1, etc. Nor could you use it to declare individual elements of an array, like logic ready_[0], ready_[1].

You have several alternatives, the easiest is declaring these ports as arrays.

`define PORTS 4
module mulitplexer
(
  input logic clock,
    output  a_t       multiplx_a_[`PORTS],
    input   a_fc_t    a_multiplx_[`PORTS],
    input   b_t       multiplx_b_[`PORTS],
    input   logic     ready_[`PORTS],
input logic reset
);

You can also create struct with these as fields, but you would need to separate the inputs form the outputs. Finally, you could find a macro pre-processor that allows you to write a `for loop as a macro. SystemVerilog does not have that built in.

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  • \$\begingroup\$ @dave_59, Hi, what if I want to do port mapping using generate? Can we do port mapping (not port declaration) using just array index? I remember using verilog preprocessor years ago (which expands loops). \$\endgroup\$
    – Chan Kim
    Commented Aug 10, 2016 at 2:50
  • \$\begingroup\$ @ChanKim Not sure what you mean. Please ask a separate question \$\endgroup\$
    – dave_59
    Commented Aug 10, 2016 at 5:46
  • \$\begingroup\$ @dave_59, I later realized I can just do normal .port(sig) when port and sig is array. (I was thinking of for loop to connect each port/signal array elements). \$\endgroup\$
    – Chan Kim
    Commented Aug 10, 2016 at 6:38
0
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Courtesy of chipverify.com:

A generate block cannot contain port, parameter, specparam declarations or specify blocks. However, other module items and other generate blocks are allowed. All generate instantiations are coded within a module and between the keywords generate and endgenerate. -- https://www.chipverify.com/verilog/verilog-generate-block

I need that for myself for instantiating 4 identical modules except direction of one port. I am getting back to you if I figure out how to do.

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