I am new here. I am trying to write VHDL codes for my FSM that has got 3 states : s0,s1,s2 At reset it comes to S0 and then if start is one goes to s2 and stays there for 12 clock cycle and then goes to s2 and then in s2 if done =1 goes to s0 again. here is my VHDL code for it but it is not compiling .
Could someone please help me out here.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity state3_fsm is port ( clk_H : in std_logic; res_H: in std_logic; start : in std_logic; done_H : in std_logic ); end entity state3_fsm; -- architecture arc of state3_fsm is type statetype is (s0,s1,s2); signal pr_state ,nx_state : statetype ; constant clock_delay_12 : integer :=12; signal s_counter : std_logic_vector(3 downto 0); begin ff_pro : process (clk_H,res_H) begin if (res_H ='1') then pr_state <= s0; elsif (clk_H'event and clk_H = '1') then pr_state <= nx_state ; end if; end process ff_pro; com_pro : process (start,s_counter,pr_state,done_H) begin case pr_state is when s0 => if (start_H = '1') then nx_state <= s1 ; else nx_state <= s0; end if; when s1 => s_counter <= s_counter + 1 ; if s_counter = clock_delay_12 then nx_state <= s2; s_counter <= '0'; else nx_state <= s1; end if; when s2 => if done_H ='1' then nx_state <=s0; else nx_state <= s2; end if; when others => nx_state <=s0; end case; end process com_pro; end architecture arc;