I am new here. I am trying to write VHDL codes for my FSM that has got 3 states : s0,s1,s2 At reset it comes to S0 and then if start is one goes to s2 and stays there for 12 clock cycle and then goes to s2 and then in s2 if done =1 goes to s0 again. here is my VHDL code for it but it is not compiling .

Could someone please help me out here.

Thank you

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity state3_fsm is
  port (
    clk_H : in std_logic;
    res_H: in std_logic;
    start : in std_logic;
    done_H : in std_logic

end entity state3_fsm;

architecture arc of state3_fsm is

  type statetype is (s0,s1,s2);
  signal pr_state ,nx_state : statetype ;
  constant clock_delay_12 : integer :=12;
  signal s_counter : std_logic_vector(3 downto 0);


  ff_pro : process (clk_H,res_H)
    if (res_H ='1') then
      pr_state <= s0;
    elsif (clk_H'event and clk_H = '1') then
      pr_state <= nx_state ;
    end if;
  end process ff_pro;

  com_pro : process (start,s_counter,pr_state,done_H)
    case pr_state is
      when s0 => 
        if (start_H = '1') then 
          nx_state <= s1 ;
          else nx_state <= s0;
            end if;
      when s1 => 
        s_counter <= s_counter + 1 ;
        if s_counter = clock_delay_12  then 
          nx_state <= s2;
          s_counter <= '0';
          else nx_state <= s1;
        end if;

      when s2 => 
        if done_H ='1' then 
          nx_state <=s0;
          nx_state <= s2;
        end if;

      when others =>
        nx_state <=s0;  

    end case;
  end process com_pro;

end architecture arc;
  • 1
    \$\begingroup\$ A counter (s_counter) can not be implemented as a combinatorical circuit. \$\endgroup\$
    – Paebbels
    Commented Sep 17, 2015 at 19:53

1 Answer 1


First, on line 9 and 34, your use start, but in the rest of the code it is used as start_H.

Second, see https://stackoverflow.com/questions/8109078/addition-in-vhdl-not-compiling for solutions to your + operator not found error on line 43.

Third, you need to make sure that both s_counter and clock_delay_12 are the same type so that you can compare them on line 44. Exactly what type will depend on your solution the + operator not found.

Fourth, line 46, ''0' is of type std_logic, s_counter is of type std_logic_vector(3 downto 0), so you would use "0000" instead. You could also use something like (others => '0')

There may also be other errors, but this as far as I got.

I also have some style comments.

On line 29, I would use rising_edge(clk_H) instead of clk_H'event and clk_H = '1'.

Your if statements don't need extra parentheses.

Like Brian Drummond said in a comment, I would avoid using the 2-process state machine, I prefer the 1-process form.

  • 2
    \$\begingroup\$ I kinda disagree with your last statement ("I would avoid using the 2-process state machine"). Instead, I would suggest to get into the habit of writing your state machines in the 2-process style. It will help you to manage complicated designs, it will also be helpful to optimize some performance limiting combinatorial part of the FSM. \$\endgroup\$
    – Ali
    Commented Sep 17, 2015 at 20:52

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