in order to explain how to a pipelined multioperand adder could be implemented my book shows the image reported below. The idea is to use three adder with 4 stage pipeline. However i tried to make a simple timing diagram by myself to check if i've understood well what my book meant, however i can't write a timed diagram so i'm quite sure i haven't understood good the concept.
So... question how that image should be interpreted? Practical example?
I report what my reference says: Figure 8.3 (the one i posted) shows that if the adder is implemented as a four-stage pipeline, then three adders can be used to achieve the maximum possible throughput of one operand per clock cycle. Even though the clock cycle is now shorter because of pipelining, the latency from the first input to the last output remains asymptotically the same with h-stage pipelining for any fixed h.