If you have byte addressable memory, does it matter if you have a 32 bit or 64 bit databus for the range of the memory addresses for the words of the memory?

E.g. : Assume a 32-bit word. If you have a processor connected to a byte addressable \$2^{32}\$ byte memory,

Would the address of the lowest word be 0 and the address of the highest word simply be \$2^{32}-4\$ (0xFFFFFFFC) regardless of whether your databus size is 32 bit or 64 bit?

What difference would it make when you assume a 64-bit word or a 16-bit word?

  • \$\begingroup\$ A 'word' is a flexible concept :( Are you sure what it means in your context? 64 bits, or 8 bits, or maybe even 8..64 bits? If a word is 32 bits, the address of the highest word cannot be 2^32 - 1! \$\endgroup\$ – Wouter van Ooijen Sep 19 '15 at 13:18
  • \$\begingroup\$ @WoutervanOoijen "If a word is 32 bits, the address of the highest word cannot be 2^32 - 1! " What would be the address of the highest word be in that case? \$\endgroup\$ – QuantumD Sep 19 '15 at 13:32
  • \$\begingroup\$ bit, 8 bit = 1 byte, 16 bit = 1 word, 32 bit = 1 double word. With 32 pins you can address 2^32 bytes = 4GB RAM. \$\endgroup\$ – Marko Buršič Sep 19 '15 at 13:58
  • \$\begingroup\$ @MarkoBuršič I think that depends of the type of processor.You assume a 16-bit processor. On a 32-bit processor: 16 bit = halfword, 32 bit = 1 word, 64 bit = double world. But how was your comment related to the question again? \$\endgroup\$ – QuantumD Sep 19 '15 at 14:23
  • \$\begingroup\$ @ QuantumD: being a teacher myself I refrain from giving the naked answer. You have all the pieces, put it together! \$\endgroup\$ – Wouter van Ooijen Sep 19 '15 at 15:52

The data bus width has no correlation to the range of memory addresses. The address bus and the data bus are separate entities.

For example, if your data bus is 32 bits wide, and your address bus is 16 bits wide, you can have 2^16 memory addresses that are each 32 bits wide. 2^16x32 = 64k x 32bits.

In my example, the lowest memory address is $0000, and the highest memory address is $FFFF. In your example, the lowest would be $00000000 and the highest would be $FFFFFFFF. Each memory address points to a group of bits (32 bits in both of our examples). If you changed your data bus width to 64 bits, and kept your address bus the same width, your memory address span would stay the same. Each address would simply point to 64 bits instead.

  • \$\begingroup\$ So, WoutervanOoijen's comment "If a word is 32 bits, the address of the highest word cannot be 2^32 - 1!" wouldn't make any sense? \$\endgroup\$ – QuantumD Sep 19 '15 at 15:18
  • \$\begingroup\$ @QuantumD No, I don't think his comment makes sense. If a system has a memory that is x bits wide, each memory address is able to hold x bits of information. \$\endgroup\$ – Tom Sep 19 '15 at 15:49
  • \$\begingroup\$ quote: "If you have byte addressable memory..." \$\endgroup\$ – Wouter van Ooijen Sep 19 '15 at 15:53
  • \$\begingroup\$ @WoutervanOoijen So what you are trying to see was something like, If you assume a 32-bit word (4 bytes), how can the address of the highest word be 2^32-1? Did you expect 2^32-4? \$\endgroup\$ – QuantumD Sep 19 '15 at 16:07
  • \$\begingroup\$ Yes. Can you explain how you arrived at that answer? \$\endgroup\$ – Wouter van Ooijen Sep 19 '15 at 16:12

1 Byte = 8 bits. So byte addressable means you can access 8 bits at a time. Number of address lines simply tells you number of locations which can be accessed. The data line width will depend upon the number of bits stored in the location. It could be 8 bits, 32 bits or 64 bits.

32 bit word means there are 4 bytes which are accessed, generally we access data in words 32 bits for each read/write process. But sometime we just want to change just few bits so system is kept as byte addressable so that we can access just a certain byte and change it. Otherwise even for a single bit change we have to access the whole 32 bits which delays the process.

We are trying to increase the bus width to 64 bits because it will allow us to read big chunk of data with each read and write hence speed up the process.

I am trying to keep things simple just increasing the data bus width doesn't necessarily increase the speed of process because it depends upon various factors.

  • \$\begingroup\$ How does this answer my question? Could you please elaborate on what your conclusion is with respect to the question? \$\endgroup\$ – QuantumD Sep 19 '15 at 15:28
  • \$\begingroup\$ If you have 32 bits of address line, it just tells you that you have 2^32 address(locations) from where data can be accessed. The width of data has nothing to do with those 32 bit address lines. Assume address lines as address of house and data lines as no. of rooms in a house. So address doesn't tell you how many rooms are there in a house. It just gives you the location of the house. The house could have different no of rooms(8,32,64) based on its architecture. \$\endgroup\$ – Prabhat Sep 19 '15 at 15:58
  • \$\begingroup\$ According to your sentence "Assume a 32-bit word. If you have a processor connected to a byte addressable 232 byte memory" \$\endgroup\$ – Prabhat Sep 21 '15 at 3:42

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