I am studying about the 8255A PPI. In Mode 0 of it, it says that the outputs are latched and inputs are not latched. What exactly does it mean?
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\$\begingroup\$ IMO it means if the input data changes during reading it can be inconsistent. Latched would mean that it is stored and during read even if input data changes you will get the input data at time they were latched, by means of RD command or... \$\endgroup\$– Marko BuršičSep 20, 2015 at 16:31
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\$\begingroup\$ There is a very good explanation in the C8051F410x datasheet of this regarding the programmable comparators. \$\endgroup\$– Balázs BörcsökMay 26, 2021 at 15:07
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\$\begingroup\$ There is a very good explanation in the C8051F410x datasheet of this regarding the programmable comparators. \$\endgroup\$– Balázs BörcsökMay 26, 2021 at 15:07
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'Latched' means the bits are put into a storage register (array of flip-flops) which holds its output constant even if the inputs change after being latched.
The 8255's outputs are latched to hold the last data written to them. This is required because the data only stays on the bus for one cycle, so without latching the outputs would become invalid as soon as the write cycle finished.
The inputs are not latched because the CPU only has to read their current values, then store the data in a CPU register or memory if it needs to be referenced at a later time. If an input changes while the port is being read then the result may be indeterminate.
answered Sep 20, 2015 at 19:09