I've a design problem in VHDL with a serial adder. The block diagram is taken from a book.

enter image description here

Since i'm not skilled enough in design with clock (except some silly flip flop i've found on the web, and similarly a register, where the design is pretty much the same) i have some problem in the design.

I would start with a register (n bit) a full adder and than a flip flop as basic component. Register and flip flop should be updated and shift for every clock cycle, the full adder is combinatorial so it is ok. I'm not sure however how the whole entity for the adder should be designed i would attempt with something like

entity adderSerial is
  generic(n : natural);
  port(x, y : in std_logic_vector(n - 1 downto 0);
       clk : in std_logic;
       z : out std_logic_vector(n - 1 downto 0));
end entity adderSerial;

The internal architecture confuse me a lot since actually i don't know how to behave in the synchronization stuff... At high level i would say probably internally should be even a counter that probably keep track of when all the bits are being processed. But i'm not sure if this is the right way to perform this design, i would like to keep as much close i can to the diagram i posted.

Any suggestion for such simple design?


Ok here i have my first attempt for the design... I splitted in three process, first process for handling the input registers, second for handling the full adder and third for handling the register z, i sync with a clock signal and i think i've written a correct sensitivity list for each process. Input signal are also clk, load and clear. Clk is the clock, load is to write the x,y value in the registers while clear is to clear registers and flip flop. Pleaaaaaaaaaase give me any feedback!!!

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;

entity serialAdder is
    generic(n : natural := 4);
    port(x : in std_logic_vector(n - 1 downto 0);
         y : in std_logic_vector(n - 1 downto 0);
         clk : in std_logic;
         load : in std_logic;
         clr : in std_logic;
         z : out std_logic_vector(n - 1 downto 0));
end entity serialAdder;

architecture arch of serialAdder is
    signal x_reg : std_logic_vector(n - 1 downto 0);
    signal y_reg : std_logic_vector(n - 1 downto 0);
    signal z_reg : std_logic_vector(n - 1 downto 0);
    signal c_reg : std_logic;
    process(clk) is --handling of registers "x" and "y", synchronous

        if rising_edge(clk) then
            if clr = '1' then --clear all the registers, and flip flop
                x_reg <= (others => '0');
                y_reg <= (others => '0');
                c_reg <= '0';
                z_reg <= (others => '0');
            elsif load = '1' then
                x_reg <= x;
                y_reg <= y;
            else --execute sum
                x_reg <= '0' & x_reg(n - 1 downto 1); --right input register shift
                y_reg <= '0' & y_reg(n - 1 downto 1);       

                --full adder logic      
                z_reg <= (x_reg(0) xor y_reg(0) xor c_reg) & z_reg(n - 1 downto 1); --right shift and adding a new bit
                c_reg <= (c_reg and x_reg(0)) or (c_reg and y_reg(0)) or (x_reg(0) and y_reg(0)); --carry update
            end if;
        end if;
    end process;

    z <= z_reg; --update of the output

end architecture arch;
  • \$\begingroup\$ I should probably put a reset signal for the registers and flip flop too, wheter i need to perform a new sum. \$\endgroup\$ Sep 21, 2015 at 11:03
  • \$\begingroup\$ Why not start with the full adder and work from there? How are you going to make the full adder? \$\endgroup\$
    – stanri
    Sep 21, 2015 at 11:17
  • \$\begingroup\$ I already have a full adder, i mean implemented, i've also implemented a ripple carry adder. But i think that in this design the actual problem is the synchronization of the all subcomponents. \$\endgroup\$ Sep 21, 2015 at 11:20
  • \$\begingroup\$ Everything should be synchronus, so it's just a matter of performing a new add every clock cycle. does your FA have a clk input? \$\endgroup\$
    – stanri
    Sep 21, 2015 at 11:22
  • 1
    \$\begingroup\$ Ok let's take in another way... i try to write single component, i put in another post eventually for correctness then i'll be back here to complete this post. \$\endgroup\$ Sep 21, 2015 at 12:21

1 Answer 1


z : out std_logic_vector(n - 1 downto 0)); The output must be std_logic, because it is a serial output

Also, you can use the + operator directly to the std_logic_vectors. Just add the "ieee.std_logic_signed" library So that you can write z_reg <= x+y;

if rising_edge(clk) then if clr = '1' then --clear all the registers, and flip flop

            c_reg <= '0';
            z_reg <= (others => '0');
        elsif load = '1' then
            z_reg <= x + y;

        else --execute sum       

            --full adder logic      
            z <=  z_reg(0);
            z_reg <= '0'& z_reg(n-1 downto 1);
        end if;
    end if;
  • \$\begingroup\$ Why would I use the + operator anyway if the purpose was to implement an adder anyway. \$\endgroup\$ Apr 19, 2018 at 9:35
  • \$\begingroup\$ @user8469759 why would you use VHDL to describe gates? \$\endgroup\$
    – DonFusili
    Apr 19, 2018 at 9:45
  • \$\begingroup\$ So you have a adder module, and you have to integrate it to generate a serial adder \$\endgroup\$
    – user186273
    Apr 19, 2018 at 10:17
  • \$\begingroup\$ what are the ports of your adder module \$\endgroup\$
    – user186273
    Apr 19, 2018 at 10:24
  • \$\begingroup\$ @DonFusili, it's not the same thing... it really isn't. \$\endgroup\$ Apr 19, 2018 at 12:23

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.